Image Processing Device and Semiconductor Device

Patent metadata

Field	Value
Publication number	US-2016227236-A1
Application number	US-201514970603-A
Country	US
Kind code	A1
Filing date	Dec 16, 2015
Priority date	Jan 30, 2015
Publication date	Aug 4, 2016
Grant date	—

Abstract

In an image processing device, a motion image decoding processing unit extracts a feature amount of a target image to be decoded from an input stream, and changes a read size of a cache fill from an external memory to a cache memory, based on the feature amount. The feature amount represents an intra macro block ratio in, for example, one picture (frames or fields), or a motion vector variation. When the intra macro block ratio is high, the read size of the cache fill is decreased.

First claim

What is claimed is:

1 . An image processing device comprising:
a motion image decoding processing unit to which a stream is input; a cache memory which temporarily stores data stored in an external memory; a cache control unit; a to-be-decoded image analyzing unit; an address control unit which outputs a request address in response to a request from the motion image decoding processing unit; a tag comparison control unit which has a tag memory; a read command control unit; and a cache line control unit, and wherein the to-be-decoded image analyzing unit extracts a feature amount of a target image to be decoded by the motion image decoding processing unit, from the stream, wherein the cache line control unit specifies a read size from the external memory to the cache memory, for the read command control unit, based on the feature amount, wherein the tag comparison control unit compares the request address and tag data held in the tag memory, and determines whether a cache hit or error has occurred, wherein, when the cache hit has occurred, the cache control unit reads data corresponding to the request address, and supplies the data to the motion image decoding processing unit, and wherein, when the cache error has occurred, the cache control unit reads data regarding a read size specified by the read command control unit from the external memory, and writes the data to the cache memory.

2 . The image processing device according to claim 1 ,
wherein the to-be-decoded image analyzing unit extracts an intra macro block ratio in entire macro blocks of one picture in the to-be-decoded image, as the feature amount, and wherein the cache line control unit decreases the read size, as the intra macro block ratio is high, and increases the read size, as the intra macro block ratio is low.

3 . The image processing device according to claim 1 ,
wherein the to-be-decoded image analyzing unit extracts a motion vector variation of one picture in the to-be-decoded image, as the feature amount, wherein the cache line control unit decreases the read size, as the motion vector variation is large, and increases the read size, as the motion vector variation is small.

4 . The image processing device according to claim 3 ,
wherein the to-be-decoded image analyzing unit divides a reference image corresponding to the to-be-decoded image into a plurality of areas based on a direction and a distance centrally about a target macro block to be decoded, measures a frequency distribution of motion vectors specifying the areas, and extracts the feature amount based on the frequency distribution.

5 . The image processing device according to claim 1 ,
wherein the motion image decoding processing unit includes a variable length encoding processing unit and an image signal processing unit performing a decoding process for a decoded result of the variable length encoding processing unit, wherein the variable length encoding processing unit and the image signal processing unit operate with a pipeline in unit of one picture, wherein the to-be-decoded image analyzing unit extracts the feature amount from the decoded result of the variable length encoding processing unit, and wherein the address control unit outputs the request address corresponding to a request from the image signal processing unit.

6 . The image processing device according to claim 1 ,
wherein the image processing device further includes encoding information processing unit to which encoding information corresponding to the stream is input, wherein the to-be-decoded image analyzing unit extracts the feature amount from the encoding information supplied through the encoding information processing unit.

7 . The image processing device according to claim 6 ,
wherein the image processing device further includes a motion image encoding unit, and wherein the motion image encoding unit supplies a stream generated by performing an encoding process for a motion image to the motion image decoding processing unit, and supplies encoding information in the encoding process to the encoding information processing unit.

8 . The image processing device according to claim 5 ,
wherein the to-be-decoded image analyzing unit extracts an intra macro block ratio of entire macro blocks of one picture in the to-be-decoded image, as the feature amount, and wherein the cache line control unit decreases the read size, as the intra macro block ratio is high, and increases the read size, as the intra macro block ratio is low.

9 . The image processing device according to claim 5 ,
wherein the to-be-decoded image analyzing unit extracts a motion vector variation of one picture in the to-be-decoded image, as the feature amount, and wherein the cache line control unit decreases the read size, as the motion vector variation is large, and increases the read size, as the motion vector variation is small.

10 . A semiconductor device:
a motion image decoding processing unit; a cache memory; and a cache configuration control unit, and the device being couplable to an external memory, and wherein the cache configuration control unit includes a to-be-decoded image analyzing unit, a cache configuration change control unit, and a cache control unit, wherein the motion image decoding processing unit reads a stream from the external memory, performs a decoding process for the read stream, and writes a decoded image generated by the decoding process to the external memory, wherein the to-be-decoded image analyzing unit extracts a feature amount of a target image to be decoded by the motion image decoding processing unit, from the stream, and wherein the cache configuration change control unit specifies a read size at time of a cache error of the cache memory, for the cache control unit, based on the feature amount.

11 . The semiconductor device according to claim 10 ,
wherein the to-be-decoded image analyzing unit extracts an intra macro block ratio of entire macro blocks of one picture in the to-be-decoded image, as the feature amount, and the cache configuration change control unit decreases the read size, as the intra macro block ratio is high, and increases the read size, as the intra macro block ratio is low.

12 . The semiconductor device according to claim 10 ,
wherein the to-be-decoded image analyzing unit extracts a motion vector variation of one picture in the to-be-decoded image, as the feature amount, and wherein the cache configuration change control unit decreases the read size, as the motion vector variation is large, and increases the read size, as the motion vector variation is small.

13 . The semiconductor device according to claim 10 ,
wherein the motion image decoding processing unit includes a variable length encoding processing unit and an image signal processing unit, wherein the variable length encoding processing unit and the image signal processing unit operate with a pipeline in unit of one picture, wherein the to-be-decoded image analyzing unit extracts the feature amount from a decoded result of the variable length encoding processing unit, and wherein the image signal processing unit performs a decoding process for the decoded result of the variable length encoding processing unit.

14 . The semiconductor device according to claim 10 ,
wherein the semiconductor device further includes an encoding information processing unit to which encoding information corresponding to the stream is input, and wherein the to-be-decoded image analyzing unit extracts the feature amount from the encoding information supplied through the encoding

Assignees

• Renesas Electronics Corp

Inventors

• Matsumoto Keisuke
• Matsubara Katsushige
• Mochizuki Seiji
• Kaya Toshiyuki
• Ueda Hiroshi

Classifications

• H04N19/159

  Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction · CPC title

• H04N19/136

  Incoming video signal characteristics or properties · CPC title

• H04N19/433

  characterised by techniques for memory access · CPC title

• H04N19/176

  the region being a block, e.g. a macroblock · CPC title

• H04N19/127

  Prioritisation of hardware or computational resources · CPC title