Cache allocation with code and data prioritization

Patent metadata

Field	Value
Publication number	US-2017192887-A1
Application number	US-201715401220-A
Country	US
Kind code	A1
Filing date	Jan 9, 2017
Priority date	Apr 7, 2015
Publication date	Jul 6, 2017
Grant date	—

Abstract

Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.

First claim

1 . An apparatus, comprising:
a cache; a cache control logic circuitry, to:
responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service, and
fulfill the cache fill request.

2 . The apparatus of claim 1 , wherein the cache is a set-associated cache comprising a plurality of sets, each set comprising a plurality of cache entries corresponding to a plurality of cache ways.

3 . The apparatus of claim 1 , wherein the capacity bit mask comprises a plurality of bits, each bit identifying a cache subset for storing a data item characterized by the request type and the class of service.

4 . The apparatus of claim 1 , further comprising:
a processing core, wherein the processing core is to tag the cache fill request with the identifier of the request type and the identifier of the class of service.

5 . The system apparatus of claim 1 , wherein the cache is at least one of: a level 2 cache incorporated into a processing core or a level 3 cache external to the processing core.

6 . The apparatus of claim 1 , further comprising:
a processing core, wherein the processing core further comprises a software-writable register to store the class of service.

7 . The apparatus of claim 1 , further comprising:
a processing core, wherein the processing core further comprises a software-writable register to store the capacity bit mask corresponding to the class of service and the request type.

8 . The apparatus of claim 1 , further comprising:
a processing core, wherein the processing core further comprises a software-readable register to notify platform software of one of: a total number of classes of service or a size of the capacity bit mask.

9 . The apparatus of claim 1 , further comprising a memory to store a data structure comprising a plurality of mappings, each mapping associating a class of service with a plurality of capacity bit masks, each capacity bit mask corresponding to a request type.

10 . A method, comprising:
receiving a cache fill request with respect to a cache, the cache fill request comprising an identifier of a request type and an identifier of a class of service; identifying a capacity bit mask associated with the request type and the identifier of the class of service; identifying a subset of the cache corresponding to the capacity bit mask; and fulfilling the cache fill request using the identified subset of the cache.

11 . (canceled)

12 . The method of claim 10 , wherein the cache is a set-associated cache comprising a plurality of sets, each set comprising a plurality of cache entries corresponding to a plurality of cache ways.

13 . The method of claim 10 , wherein the capacity bit mask comprises a plurality of bits, each bit of a pre-defined value identifying a cache subset for storing a data item characterized by the request type and the class of service.

14 . The method of claim 10 , wherein identifying the capacity bit mask comprises:
performing lookup in a memory data structure comprising a plurality of mappings, each mapping associating a class of service with a plurality of capacity bit masks, each capacity bit mask corresponding to a request type.

15 . An integrated circuit comprising:
a cache control logic circuitry, the cache control logic circuitry to:
receive a cache fill request with respect to a cache, the cache fill request comprising an identifier of a request type and an identifier of a class of service;
identify a capacity bit mask associated with the request type and the class of service; and
identify a subset of the cache corresponding to the capacity bit mask.

16 . The integrated circuit of claim 15 , wherein the cache control logic circuitry is further to:
fulfil the cache fill request using the identified subset of the cache.

17 . The integrated circuit of claim 15 , wherein the cache is a set-associated cache comprising a plurality of sets, each set comprising a plurality of cache entries corresponding to a plurality of cache ways.

18 . The integrated circuit of claim 15 , wherein the capacity bit mask comprises a plurality of bits, each bit identifying a cache subset to allocate for storing a data item characterized by the request type and the class of service.

19 . The integrated circuit of claim 15 , wherein to identify the capacity bit mask, the cache control logic circuitry is further to:
perform lookup in a memory data structure comprising a plurality of mappings, each mapping associating a class of service with a plurality of capacity bit masks, each capacity bit mask corresponding to a request type.

20 . The integrated circuit of claim 15 , wherein the memory data structure is stored in the cache.

21 . The integrated circuit of claim 15 , wherein the cache is at least one of: a level 2 cache incorporated into a processing core or a level 3 cache external to the processing core.

Assignees

• Intel Corp

Inventors

• Herdrich Andrew J
• Verplanke Edwin
• Iyer Ravishankar
• Gianos Christopher C
• Chamberlain Jeffrey D
• Singhal Ronak
• Mandelblat Julius
• Toll Bret L

Classifications

• G06F12/084 Primary

  with a shared cache · CPC title

• G06F12/0842

  for multiprocessing or multitasking · CPC title

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F12/0804 Primary

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title