Semiconductor packages and methods of manufacturing thereof

Patent metadata

Field	Value
Publication number	US-11502012-B2
Application number	US-202017082643-A
Country	US
Kind code	B2
Filing date	Oct 28, 2020
Priority date	Jan 28, 2020
Publication date	Nov 15, 2022
Grant date	Nov 15, 2022

Abstract

Semiconductor packages described herein include a thermal capacitor designed to absorb transient heat pulses from a power semiconductor die and subsequently release the transient heat pulses to a surrounding environment, and/or a recessed pad feature. Corresponding methods of production are also described.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a substrate having a first main surface, a second main surface opposite the first main surface, an electrically insulating core between the first and second main surfaces, and an electrically conductive first via extending through a periphery region of the core, the periphery region defining an opening in the core;
a power semiconductor die embedded in the opening in the core, the power semiconductor die being thinner than or a same thickness as the core, the power semiconductor die comprising a first load terminal bond pad at a first side which faces a same direction as the first main surface of the substrate, a second load terminal bond pad at a second side which faces a same direction as the second main surface of the substrate, and a control terminal bond pad at the first side or the second side;
a plated first contact pad at the second main surface of the substrate and provided by the first via;
a plated second contact pad at the second main surface of the substrate and provided by the second load terminal bond pad of the power semiconductor die; and
a thermal capacitor attached to the first main surface of the substrate, the thermal capacitor designed to absorb transient heat pulses from the power semiconductor die and subsequently release the transient heat pulses to a surrounding environment.

2. The semiconductor package of claim 1 , wherein a thickness of the thermal capacitor is based on a magnitude of the transient heat pulses.

3. The semiconductor package of claim 2 , wherein the magnitude of the transient heat pulses is in a range of 5 to 25 Joules, and wherein the thickness of the thermal capacitor is in a range of 500 to 2500 μm.

4. The semiconductor package of claim 1 , wherein a first metallization at the first main surface of the substrate electrically connects the first load terminal bond pad of the power semiconductor die to the first via, and wherein the thermal capacitor is attached to the first metallization or to a plated surface of the first metallization.

5. The semiconductor package of claim 1 , wherein the thermal capacitor is attached to the first via and to the first load terminal bond pad of the power semiconductor die, and wherein the thermal capacitor electrically connects the first load terminal bond pad to the first via.

6. The semiconductor package of claim 1 , wherein the thermal capacitor has lateral dimensions that are less than the lateral dimensions of the core such that a border of the thermal capacitor is spaced inward from a border of the core.

7. The semiconductor package of claim 1 , wherein the thermal capacitor is attached to the first main surface of the substrate by solder, and wherein a border of the thermal capacitor has a protrusion that prevents the solder from reaching a surface of the thermal capacitor that faces away from the substrate.

8. The semiconductor package of claim 1 , wherein a surface of the thermal capacitor that faces away from the substrate is structured to increase surface contact with the surrounding environment.

Assignees

• Infineon Technologies Ag

Inventors

• Cho Eung San
• Naeve Tomasz
• Palm Petteri

Classifications

• H10W70/635

  Through-vias · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title