Cavity generation for embedded interconnect bridges utilizing temporary structures

Patent metadata

Field	Value
Publication number	US-10170428-B2
Application number	US-201615197577-A
Country	US
Kind code	B2
Filing date	Jun 29, 2016
Priority date	Jun 29, 2016
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

Embodiments are generally directed to cavity generation for an embedded interconnect bridge utilizing a temporary structure. An embodiment of a package includes a substrate; a silicon interconnect bridge including a plurality of interconnections, the interconnect bridge being embedded in the substrate; and a plurality of contacts on a surface of the substrate, the plurality of contacts being coupled with the plurality of interconnections of the interconnect bridge. The interconnect bridge is bonded in a cavity in the substrate, the cavity being formed by removal of at least one temporary structure from the substrate.

First claim

What is claimed is:

1. A method comprising:
fabricating a package substrate;
placing at least one temporary structure in a first location on the package substrate;
subsequent to placing the at least one temporary structure in the first location on the package substrate, applying a first dielectric material to the package substrate, to surround at least a portion of the at least one temporary structure;
subsequent to applying the first dielectric material to the package substrate, removing the at least one temporary structure from the package substrate to generate a cavity in the package substrate, wherein a portion of the first dielectric material remains over the cavity subsequent to removing the temporary structure;
removing the portion of the first dielectric material from over the cavity;
subsequent to removing the portion of the first dielectric material from over the cavity, bonding an interconnect bridge in the cavity, the interconnect bridge including a plurality of interconnections;
applying a second dielectric material to the package substrate; and
installing a plurality of contacts to a surface of the package substrate, the plurality of contacts being coupled with the interconnect bridge.

2. The method of claim 1 , wherein removing the at least one temporary structure includes applying a condition to change a form of the at least one temporary structure.

3. The method of claim 2 , wherein the at least one temporary structure includes a volume of sacrificial material.

4. The method of claim 3 , wherein applying the at least one temporary structure includes stencil-printing or photo-defining the sacrificial material.

5. The method of claim 3 , wherein the sacrificial material includes a sacrificial polymer.

6. The method of claim 3 , wherein removing the at least one temporary structure include decomposing the sacrificial material to generate the cavity in the first location.

7. The method of claim 6 , wherein decomposing the sacrificial material includes applying a decomposition condition to the package substrate.

8. The method of claim 7 , wherein applying the decomposition condition to the package substrate includes applying a thermal condition to the package substrate.

9. The method of claim 1 , further comprising removing remaining dielectric material subsequent to removing the at least one temporary structure.

10. The method of claim 9 , wherein removing remaining dielectric material includes performing laser drilling to remove remaining dielectric material subsequent to removing the at least one temporary structure.

11. The method of claim 9 , further comprising performing laser cutting of the dielectric material prior to removing the at least one temporary structure.

12. The method of claim 11 , wherein removing remaining dielectric material includes picking dielectric material from the cavity subsequent to removing the at least one temporary structure.

Assignees

• Intel Corp

Inventors

• Pietambaram Srinivas V
• Manepalli Rahul N

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/255

  of outermost layers of multilayered bumps, e.g. material of a coating · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title