Wafer level proximity sensor

US11069667B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11069667-B2
Application numberUS-201615087959-A
CountryUS
Kind codeB2
Filing dateMar 31, 2016
Priority dateMar 31, 2016
Publication dateJul 20, 2021
Grant dateJul 20, 2021

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer, forming an interconnect structure of through-silicon vias within the substrate, and singulating the bonded wafers to yield individually packaged sensors. The wafer level proximity sensor is smaller than a conventional proximity sensor and can be manufactured using a shorter fabrication process at a lower cost. The proximity sensors are coupled to external components by a signal path that includes the through-silicon vias and a ball grid array formed on a lower surface of the silicon substrate. The design of the wafer level proximity sensor passes more light from the light emitter and more light to the light sensor.

First claim

Opening claim text (preview).

The invention claimed is: 1. A package, comprising: a first outer surface; a second outer surface; a thinned silicon substrate having a first surface and a second surface opposite the first surface, the second outer surface being formed by the second surface of the thinned silicon substrate; a plurality of through silicon vias extending through the thinned silicon substrate, the plurality of through silicon vias extending from the first surface to the second surface, end surfaces of the plurality of through silicon vias being at the second surface and being coplanar with the second surface; a light sensor in the first surface of the silicon substrate; a contact pad in the first surface of the silicon substrate; a light emitter structurally and electrically coupled to the contact pad; and a cap of silicon having a first surface and a second surface that is opposite to the first surface, the first surface of the cap being bonded to the first surface of the silicon substrate, the first outer surface being formed in part by the second surface of the cap, the cap of silicon including: a first opening over the light emitter, the first opening extending completely through the cap and having a width adjacent the light emitter that is greater than a width of the light emitter, the contact pad being within the first opening; and a second opening over the light sensor, the second opening having a width substantially equal to a width of the light sensor; a transparent epoxy material in the first opening and the second opening, the transparent epoxy material in each of the first and second openings having a surface substantially co-planar with the second surface of the cap of silicon, the first outer surface including the second surface of the cap of silicon and the surfaces of the transparent epoxy material, the transparent epoxy material being directly on and physically coupled to the light sensor, the light emitter, and the contact pad; and a plurality of solder balls on the second surface of the thinned silicon substrate, the plurality of solder balls are electrically and physically coupled to the end surfaces of ones of the plurality of through silicon vias. 2. The package of claim 1 wherein: the thinned silicon substrate has a first dimension that extends from the first surface of the thinned silicon substrate to the second surface of the thinned silicon substrate, the first dimension is in the range of 0.2 and 0.3 millimeters; and the cap of silicon has a second dimension extending between the first surface of the cap of silicon and the second surface of the cap of silicon, the second dimension is in the range of 0.2 and 0.3 millimeters. 3. The package of claim 1 wherein the cap of silicon is bonded to the silicon substrate by an epoxy bonding layer having a thickness in the range of 0.5 and 0.15 micrometers. 4. The package of claim 1 wherein the light emitter is a light emitting diode mounted directly on the contact pad. 5. The package of claim 1 wherein the light emitter is a laser diode on the contact pad. 6. The package of claim 1 wherein a thickness of the bonded cap of silicon and silicon substrate is less than 0.7 millimeters. 7. The package of claim 1 wherein the cap of silicon provides a light barrier between the first opening and the second opening. 8. The package of claim 1 , further comprising: at least a first one of the plurality of through silicon vias electrically connects the light sensor to a first solder ball of the plurality of solder balls; and at least a second one of the plurality of through silicon vias electrically connects the contact pad to a second solder ball of the plurality of solder balls. 9. A device, comprising: a package that includes a first outer surface opposite to a second outer surface and a first outer edge opposite to a second outer edge, the package including: a thinned silicon substrate having a first surface and a second surface, the second surface being a back-grinded surface; a light sensor at the first surface of the silicon substrate, the light sensor having a third surface substantially co-planar with the first surface of the silicon substrate; a first contact pad at the first surface of the silicon substrate, the first contact pad being spaced from the light emitter; a light emitter coupled to the first contact pad; a second contact pad at the second surface of the silicon substrate; a cap bonded to the first surface of the silicon substrate, the cap having a fourth surface facing away from the silicon substrate, the cap including a first opening aligned with and exposing the light emitter and a second opening aligned with and exposing the light sensor; a first transparent material in the first opening and directly on the light emitter, the first transparent material filling the first opening and being coplanar with the fourth surface of the cap, the first transparent material covering and being physically coupled to a surface of the first contact pad; and a second transparent material in the second opening, the second transparent material is directly on and physically coupled to the light sensor, the second transparent material filling the second opening and being coplanar with the fourth surface of the cap, the first outer surface of the package being the fourth surface of the cap and the coplanar surfaces of the first and second transparent materials, the second outer surface of the package being the back-grinded second surface of the thinned silicon substrate, and the first and second outer edges of the package being coplanar edges of the cap and the silicon substrate. 10. The device of claim 9 wherein the light emitter is an LED. 11. The device of claim 9 wherein the cap is a silicon cap that is bonded to the silicon substrate at three locations. 12. The device of claim 11 wherein the three locations include a position adjacent to the first contact pad, a position between the first contact pad and the light sensor and a position adjacent to the light sensor. 13. The device of claim 9 wherein the electrical connection is a silicon through hole. 14. The device of claim 9 , further comprising: at least one solder ball coupled to the second contact pad; and an electrical connection extending from the first contact pad to the second contact pad and integrated with the silicon substrate. 15. The device of claim 9 , wherein the first opening has a constant width through the cap that is greater than the width of the light emitter. 16. A wafer level proximity micro-sensor module, comprising: a back-grinded silicon substrate having a first surface opposite a second surface; a light sensor at the first surface of the back-grinded silicon substrate, the light sensor including a surface substantially co-planar with the first surface of the back-grinded silicon substrate; a first contact pad at the first surface of the silicon substrate; a light emitter coupled to the first contact pad; a cap coupled to the first surface of the silicon substrate, the cap including a third surface opposite to the first surface of the silicon substrate, a first opening aligned with the light emitter and a second opening aligned with the light sensor, the first opening having a width proximate the light emitter that is greater than a width of the light emitter; and a first transparent portion fills the first opening and covers the light emitter, a second transparent portion fills the second opening and covers the light sensor, the first transparent portion has a fourth surface, the second transparent portion has a fifth surface, an

Assignees

Inventors

Classifications

  • the interconnections being through-semiconductor vias · CPC title

  • Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

  • Packaging processes not covered by the other groups of this subclass · CPC title

  • H10W90/00Primary

    Package configurations · CPC title

  • for devices having potential barriers · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11069667B2 cover?
Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer, forming an interconnect structure of through-silicon vias within the substrate, and singulating the bonded wafers to yield individually packaged sensors. The wafer level proximity sensor is smaller than a conventional proximity sensor…
Who is the assignee on this patent?
St Microelectronics Pte Ltd
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 20 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).