Implementing logic function and generating analog signals using NOR memory strings

Patent metadata

Field	Value
Publication number	US-11488676-B2
Application number	US-202117394733-A
Country	US
Kind code	B2
Filing date	Aug 5, 2021
Priority date	Sep 30, 2015
Publication date	Nov 1, 2022
Grant date	Nov 1, 2022

Abstract

NOR memory strings may be used for implementations of logic functions involving many Boolean variables, or to generate analog signals whose magnitudes are each representative of the bit values of many Boolean variables. The advantage of using NOR memory strings in these manners is that the logic function or analog signal generation may be accomplished within one simultaneous read operation on the NOR memory strings.

First claim

We claim:

1. A method for implementing a logic function involving first and second sets of Boolean variables, comprising:
associating each Boolean variable in the first set to a selected one of a plurality of memory cells in at least one NOR memory string, each NOR memory string providing an output value representing whether or not at least one of its memory cell is in a conducting state during a read operation;
programming each selected memory cell according to the value of the associated Boolean variable;
associating each Boolean variable in the second set to one of the selected memory cells in the NOR memory string according to the logic function to be implemented; and
selectively reading the selected memory cells that are associated with Boolean variables of both the first set and the second set, each memory cell being read or not read according to the value of the associated Boolean variable in the second set.

2. The method of claim 1 , wherein each selected memory cell in a first one of the at least one NOR memory string is programmed to a conducting state, when the associated Boolean variable in the first set has a ‘0’ value and to a non-conducting state, when the associated Boolean variable in the second set has a ‘1’ value.

3. The method of claim 2 , further comprising programming the selected memory cells in a second one of the at least one NOR memory string, wherein each selected memory cell in the second NOR memory string is programmed to a non-conducting state, when the associated Boolean variable in the first set has a ‘0’ value and to a conducting state, when the associated Boolean variable in the second set has a ‘1’ value, and wherein the output values of the first and second NOR memory together provides an output value of the logic function.

4. The method of claim 3 , wherein the first and second NOR memory strings implement a match circuit in a content addressable memory.

5. In a memory circuit under control of a system controller, a method for rapidly determining the location of a file, comprising:
associating the file with a timestamp and a unique identifier index number when the file is stored or updated in the memory circuit, and storing in a look-up table in the memory circuit the associated timestamp and an address associated with where the file is stored;
receiving from the system controller a search request that specifies a unique identifier index number of a file to be located; and
using first and second NOR memory string to implement a logic function that compares the unique identifier index number in the search request with the unique identifier index number stored in the look-up table, and reporting to the system controller, when a match is found between the unique identifier index number in the search request and the unique identifier index number stored in the look-up table, the timestamp and address associated with the match.

6. The method of claim 5 , wherein the logic function is implemented by:
associating each bit of the unique identifier index number of the look-up table with a selected one of a plurality of memory cells in each of the first and second NOR memory strings, each NOR memory string providing an output value representing whether or not at least one of its memory cell is in a conducting state during a read operation;
programming each selected memory cell according to the value of the associated bit of the unique identifier of the look-up table, wherein (a) each selected memory cell in the first NOR memory string is programmed to a conducting state, when the associated Boolean variable in the first set has a ‘0’ value and to a non-conducting state, when the associated Boolean variable in the second set has a ‘1’ value; and (b) each selected memory cell in the second NOR memory string is programmed to a non-conducting state, when the associated Boolean variable in the first set has a ‘0’ value and to a conducting state, when the associated Boolean variable in the second set has a ‘1’ value, and wherein the output values of the first and second NOR memory together provides an output value of the logic function.
associating each bit of the unique identifier index number in the search request according to the logic function to be implemented; and
selectively reading the selected memory cells that are associated with the bits in both the unique identifier index numbers of the look-up table and the search request, each memory cell being read or not read according to the value of the associated bit of the unique identifier index number of the search request.

7. The method of claim 5 wherein, when more than one match is found, reporting to the system controller the timestamp and address associated with each match.

8. The method of claim 5 , wherein the system controller generates each unique identifier index number.

9. The method of claim 5 , further comprising receiving the unique identifier index number from the system controller with each storing or updating of the file.

10. The method of claim 5 , wherein the memory circuit comprises a data integrity circuit which, upon detecting an error in the memory circuit, communicates the error to an on-chip error-correcting circuitry or to the system controller, thereby enabling the on-chip error-correcting circuitry or the system controller to carry out a data recovery and program-refresh operation.

11. The method of claim 5 , wherein the memory circuit comprises an interface circuit that allows direct access using one or more conventional DRAM, SRAM, NOR flash, NAND flash, Flash solid state drive, word-wide or serial bit steaming protocols.

12. The method of claim 5 , further comprising performing a read-refresh or program-refresh operation on a portion of the memory circuit in a background mode, while carrying out concurrently read, program, or erase operations in a second portion of the memory circuit and powering down a third portion of the memory circuit.

Assignees

• Sunrise Memory Corp

Inventors

• Salahuddin Sayeef
• Norman Robert D
• Harari Eli

Classifications

• G11C16/3431 Primary

  Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title