Vertical TFT with tunnel barrier

Patent metadata

Field	Value
Publication number	US-9230985-B1
Application number	US-201414515054-A
Country	US
Kind code	B1
Filing date	Oct 15, 2014
Priority date	Oct 15, 2014
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A vertically oriented thin film transistor (TFT) having a tunnel barrier is disclosed. The tunnel barrier may be formed from a dielectric such as silicon oxide or hafnium oxide. The vertically oriented TFT selection device with tunnel barrier may serve as a selection device in a 3D memory array. The vertically oriented TFT may be used to connect/disconnect a global bit line to/from a vertical bit line in a 3D memory array. The vertically oriented TFT may be used to connect/disconnect a source line to/from a channel of a vertical NAND string in a 3D memory array. A vertical TFT with tunnel barrier has a high breakdown voltage, low leakage current, and high on current. The tunnel barrier can be at the top junction or bottom junction of the TFT.

First claim

What is claimed is:

1. A semiconductor device comprising:
a lower conductor;
an upper conductor above the lower conductor; and
a vertical thin film transistor (TFT) between the lower conductor and the upper conductor, the vertical TFT comprising:
a first source/drain region having a first conductivity, wherein the first source/drain region is in electrical contact with the lower conductor;
a second source/drain region having the first conductivity, wherein the second source/drain region is in electrical contact with the upper conductor;
a channel region between the first source/drain region and the second source/drain region, the channel region having a second conductivity; and
a tunnel barrier that comprises an insulator between either first source/drain region and the channel region or the second source/drain region and the channel region.

2. The semiconductor device of claim 1 , further comprising a three-dimensional memory array having non-volatile storage elements, the upper conductor is coupled to a group of the non-volatile storage elements.

3. The semiconductor device of claim 2 , wherein the lower conductor is a global bit line and the upper conductor is a vertical bit line.

4. The semiconductor device of claim 2 , wherein the three-dimensional memory array comprises a word line, and wherein the vertical TFT further comprises a gate adjacent to the channel region, wherein the gate is in electrical contact with the word line.

5. The semiconductor device of claim 2 , wherein the three-dimensional memory comprises vertical NAND strings that comprise the non-volatile storage elements, wherein the lower conductor is a common source line and the upper conductor is channel of a first of the NAND strings.

6. The semiconductor device of claim 1 , wherein the insulator comprises silicon oxide.

7. The semiconductor device of claim 1 , wherein the first source/drain region is heavily doped, the second source/drain region is heavily doped, and the channel region is lightly doped or intrinsic.

8. A method for forming a semiconductor device, the method comprising:
forming a lower conductor;
forming a vertically oriented thin film transistor (TFT), comprising:
forming a first semiconductor region having a first conductivity over and in electrical contact with the lower conductor;
forming a tunnel barrier over the first semiconductor region, wherein the tunnel barrier comprises an insulator;
forming a second semiconductor region having a second conductivity over the tunnel barrier;
forming a third semiconductor region having the first conductivity over the second semiconductor region; and
forming a gate adjacent to the second semiconductor region; and

forming an upper conductor over and in electrical contact with the third semiconductor region.

9. The method of claim 8 , wherein:
forming the first semiconductor region comprises forming a first region of silicon that is heavily doped;
forming the second semiconductor region comprises forming a second region of silicon that is lightly doped or intrinsic; and
forming the third semiconductor region comprises forming a third region of silicon that is heavily doped.

10. The method of claim 8 , further comprising forming a three-dimensional memory array having non-volatile storage elements, wherein forming the upper conductor comprises forming a vertically oriented conductive region coupled to a group of the non-volatile storage elements.

11. The method of claim 10 , wherein forming the lower conductor comprises forming a global bit line and wherein forming the upper conductor comprises forming a vertical bit line.

12. The method of claim 10 , wherein forming the three-dimensional memory comprises forming vertical NAND strings that comprise the non-volatile storage elements, wherein forming the lower conductor comprises forming a common source line and forming the upper conductor comprises forming a channel of a first of the NAND strings.

13. The method of claim 10 , further comprising forming a plurality of word lines in the memory array, wherein forming the gate comprises forming the gate in electrical contact with a first of the word lines.

14. The method of claim 8 , wherein forming the tunnel barrier comprises forming the insulator from silicon oxide.

15. The method of claim 8 , wherein forming the tunnel barrier comprises forming the insulator from hafnium oxide.

16. A non-volatile storage system, comprising:
a substrate;
a three dimensional memory array of memory cells positioned above the substrate;
a plurality of word lines coupled to the memory cells;
a plurality of global bit lines;
a plurality of vertically oriented bit lines coupled to the memory cells; and
a plurality of vertically oriented thin film transistor (TFT) select devices, the vertically oriented TFT select devices are coupled between the vertically oriented bit lines and the global bit lines;
each of the vertically oriented TFT select devices comprising:
a first semiconductor region having a first conductivity, wherein the first semiconductor region is in electrical contact with a first of the global bit lines;
a second semiconductor region having a second conductivity;
a third semiconductor region having the first conductivity, wherein the third semiconductor region is in electrical contact with a first of the vertical bit lines, wherein the second semiconductor region is between the first semiconductor region and the second semiconductor region;
a tunnel barrier between either the first semiconductor region and the second semiconductor region or between the third semiconductor region and the second semiconductor region, wherein the tunnel barrier comprises an insulator; and
a gate adjacent to the second semiconductor region.

17. The non-volatile storage system of claim 16 , wherein the first semiconductor region is heavily doped, the second semiconductor region is lightly doped or intrinsic, and the third semiconductor region is heavily doped.

18. The non-volatile storage system of claim 16 , wherein the tunnel barrier is between the first semiconductor region and the second semiconductor region.

19. The non-volatile storage system of claim 16 , wherein the tunnel barrier is between the third semiconductor region and the second semiconductor region.

20. The non-volatile storage system of claim 16 , wherein the first semiconductor region, the second semiconductor region, and the third semiconductor region each comprise silicon, the tunnel barrier comprises silicon oxide.

Assignees

• Sandisk 3D Llc

Inventors

• Wu Ming-Che
• Rabkin Peter
• Chen Tim

Classifications

• H10D62/165

  Tunnel injectors · CPC title

• H10D30/6728

  Vertical TFTs · CPC title

• H10D30/6713 Primary

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H01L27/1157

  Electricity · mapped topic