Stacked magnetoresistive structures and methods therefor

Patent metadata

Field	Value
Publication number	US-11488647-B2
Application number	US-201917255915-A
Country	US
Kind code	B2
Filing date	Jun 27, 2019
Priority date	Jun 28, 2018
Publication date	Nov 1, 2022
Grant date	Nov 1, 2022

Abstract

Aspects of the present disclosure are directed to magnetic tunnel junction (MTJ) structures comprising multiple MTJ bits connected in series. For example, a magnetic tunnel junction (MTJ) stack according to the present disclosure may include at least a first MTJ bit and a second MTJ bit stacked above the first MTJ bit, and a resistance state of the MTJ stack may be read by passing a single read current through both the first MTJ bit and the second MTJ bit.

First claim

What is claimed is:

1. A magnetic tunnel junction (MTJ) stack, comprising:
a first MTJ bit comprising:
a first fixed magnetic layer;
a first free magnetic layer disposed above the first fixed magnetic layer;
a first ferromagnetic layer disposed above the first free magnetic layer;
a first intermediate region disposed between the first fixed magnetic layer and the first free magnetic layer; and
a second intermediate region disposed between the first free magnetic layer and the first ferromagnetic layer; and

a second MTJ bit stacked above the first MTJ bit,
wherein the second MTJ bit comprises:
the first ferromagnetic layer;
a second free magnetic layer disposed above the first ferromagnetic layer;
a third intermediate region disposed between the second free magnetic layer and the first ferromagnetic layer; and
a fourth intermediate region disposed above the second free magnetic layer, and

wherein a resistance state of the MTJ stack is configured to be read by passing a single read current through both the first MTJ bit and the second MTJ bit.

2. The MTJ stack of claim 1 , wherein the first MTJ bit has a critical current different from a critical current of the second MTJ bit.

3. The MTJ stack of claim 1 , further comprising:
a third MTJ bit stacked above the second MTJ bit,
wherein the third MTJ bit has a critical current different from a critical current of the second MTJ bit and a critical current of the first MTJ bit.

4. The MTJ stack of claim 1 ,
wherein the first MTJ bit has a dual spin filter configuration, and
wherein the first MTJ bit has a lower critical current than a critical current of the second MTJ bit.

5. The MTJ stack of claim 3 , further comprising:
a nonmagnetic region disposed between the third MTJ bit and the second MTJ bit.

6. The MTJ stack of claim 1 , wherein a write current of the second MTJ bit is lower than a critical current of the first MTJ bit.

7. The MTJ stack of claim 1 , wherein each of the intermediate regions comprise one or more oxide layers.

8. A magnetic tunnel junction (MTJ) stack, comprising:
a plurality of vertically stacked MTJ bits configured to be read by a single read current, wherein the plurality of vertically stacked MTJ bits includes n MTJ bits, and the MTJ stack has n+1 resistance states;
wherein the plurality of vertically stacked MTJ bits includes a first MTJ bit and a second MTJ bit, and the first MTJ bit comprises:
a first fixed magnetic layer;
a first free magnetic layer disposed above the first fixed magnetic layer; and
a first ferromagnetic layer disposed above the first free magnetic layer;
a first intermediate region disposed between the first fixed magnetic layer and the first free magnetic layer; and
a second intermediate region disposed between the first free magnetic layer and the first ferromagnetic layer; and

wherein the second MTJ bit comprises:
the first ferromagnetic layer;
a second free magnetic layer, the second free magnetic layer being disposed above the first ferromagnetic layer;
a third intermediate region disposed between the second free magnetic layer and the first ferromagnetic layer; and
a fourth intermediate region disposed above the second free magnetic layer.

9. The MTJ stack of claim 8 , wherein a write current for each MTJ bit is approximately equal to a write current for each other MTJ bit.

10. The MTJ stack of claim 8 , wherein the plurality of vertically stacked MTJ bits comprises at least three MTJ bits.

11. The MTJ stack of claim 8 , wherein during a write operation, a write current is configured to pass through a diode in a low bias state and at least one MTJ bit.

12. A method of writing a resistance state to a magnetic tunnel junction (MTJ) stack including a plurality of stacked MTJ bits, the method comprising:
directing a current pattern through every MTJ bit of the plurality of stacked MTJ bits;
detecting a first resistance state of the MTJ stack by applying a read current to the MTJ stack;
switching, using the current pattern, the MTJ stack from the first resistance state to a desired resistance state.

13. The method of claim 12 , wherein a write current for each MTJ bit has a magnitude different from a write current for each other MTJ bit, and the switching the MTJ stack comprises switching a resistance state of one MTJ bit without switching all resistance states of all MTJ bits.

14. The method of claim 12 , wherein the switching the MTJ stack comprises switching a resistance state of one MTJ bit from antiparallel to parallel, and then from parallel to antiparallel.

15. The method of claim 12 , wherein a first MTJ bit of the plurality of stacked MTJ bits has a lower write current than a second MTJ bit of the plurality of stacked MTJ bits, and wherein the switching the MTJ stack comprises switching a resistance state of the first MTJ bit after switching a resistance state of the second MTJ bit.

16. The method of claim 12 , wherein the MTJ stack includes at least three MTJ bits and the read current is a second read current, and the method further comprises:
detecting an initial resistance state of the MTJ stack by applying a first read current to the MTJ stack; and
selecting the current pattern based on the detected initial resistance state.

Assignees

• Everspin Technologies Inc

Inventors

• Sun Jijun
• Mancoff Frederick
• Janesky Jason
• Conley Kevin
• Hui Lu
• Ikegawa Sumio

Classifications

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/1673

  Reading or sensing circuits or methods · CPC title

• G11C11/5607

  using magnetic storage elements · CPC title

• G11C2211/5615

  Multilevel magnetic memory cell using non-magnetic non-conducting interlayer, e.g. MTJ · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title