Memory controller and method-controlling suspend mode

Patent metadata

Field	Value
Publication number	US-11487576-B2
Application number	US-202117318554-A
Country	US
Kind code	B2
Filing date	May 12, 2021
Priority date	Feb 12, 2019
Publication date	Nov 1, 2022
Grant date	Nov 1, 2022

Abstract

A memory controller is disclosed. The memory controller is configured to control the execution of a suspend operation by a memory device. The memory controller includes: a processor configured to output an operation control signal when the memory device is performing a program/erase operation; and a suspend operation manager configured to output suspend mode change information based on the operation control signal and suspend information, wherein the processor is further configured to control the memory controller such that the memory controller outputs a suspend mode change command and a suspend command based on the suspend mode change information.

First claim

What is claimed is:

1. A solid state drive (SSD) comprising:
a first memory configured to perform a suspend operation based on a plurality of suspend modes including a first suspend mode and a second suspend mode; and
a controller configured to receive a read request from an external device, and configured to provide a suspend command and a suspend mode change command to the first memory in response to the read request while the first memory performs a program operation or an erase operation,
wherein the first memory is configured to select one of the plurality of suspend modes based on the suspend mode change command, and configured to selectively suspend the program operation or the erase operation based on the selected one of the plurality of suspend modes in response to the suspend command.

2. The SSD of claim 1 , wherein, in the first suspend mode, the first memory executes a read operation after the first memory immediately suspends the program operation or the erase operation.

3. The SSD of claim 1 , wherein, in the second suspend mode, the first memory executes a read operation, after the first memory completes a current program operation or a current erase operation and before the first memory begins a next program operation or a next erase operation.

4. The SSD of claim 3 , wherein the first memory performs the program operation or the erase operation in units of a memory page.

5. The SSD of claim 3 , wherein the first memory performs the program operation or the erase operation in units of a memory block.

6. The SSD of claim 3 , wherein the first memory performs the program operation or the erase operation in units of a memory plane.

7. The SSD of claim 3 , wherein the first memory performs the program operation or the erase operation in units of a memory chip.

8. The SSD of claim 1 , further comprising a second memory coupled to the controller,
wherein the first memory communicates with the controller via a first channel, and the second memory communicates with the controller via a second channel.

9. The SSD of claim 1 , wherein the controller includes a suspend operation manager configured to generate suspend mode change information based on suspend information associated with a requested suspend operation to be performed by the first memory.

10. The SSD of claim 1 , wherein the first memory is a non-volatile memory.

11. The SSD of claim 1 , wherein the controller includes a processor coupled to the first memory.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Sng-Hoon
• Kim In-Soo
• Kim Jong-Won
• Moon Sang-Kwon

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/7207

  management of metadata or control data · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F9/485 Primary

  Task life-cycle, e.g. stopping, restarting, resuming execution (G06F9/4881 takes precedence) · CPC title

• G06F3/0614

  Improving the reliability of storage systems · CPC title