Memory device including concurrent suspend states for different operations

Patent metadata

Field	Value
Publication number	US-2018024772-A1
Application number	US-201615216097-A
Country	US
Kind code	A1
Filing date	Jul 21, 2016
Priority date	Jul 21, 2016
Publication date	Jan 25, 2018
Grant date	—

Abstract

Some embodiments include apparatuses and methods using memory cells and a control unit to suspend an erase operation performed on a first portion of the memory cells and to suspend a program operation performed on a second portion of the memory cells while the erase operation is suspended. The control unit includes register circuitry to store status information indicating that the program operation is suspended while the erase operation is suspended.

First claim

1 . An apparatus comprising:
memory cells; and a control unit to suspend an erase operation performed on a first portion of the memory cells and to suspend a program operation performed on a second portion of the memory cells if a read command is received while the program operation is performed and while the erase operation is suspended, the control unit including register circuitry to store status information indicating that the program operation is suspended while the erase operation is suspended, the control unit to ignore an erase suspense command to suspend an in-progress erase operation if the in-progress operation exceeds a finish threshold, and the control unit to ignore a program suspend command if the program suspend command is received while the program operation is performed and while the erase operation is suspended.

2 . The apparatus of claim 1 , wherein the control unit is to perform a read operation on a third portion of the memory cells while the erase operation and the program operation are suspended.

3 . The apparatus of claim 2 , wherein the control unit is to resume the program after the read operation is completed.

4 . The apparatus of claim 2 , wherein the control unit is to resume the erase operation after the program operation is completed.

5 . The apparatus of claim 1 , wherein the control unit is to prevent an additional erase operation to be performed on the memory array while the erase operation and the program operation are suspended.

6 . An apparatus comprising:
conductive lines; memory cells; a command decoder to decode information received from the conductive lines in order to provide commands associated with operations to be performed on the memory cells; a state machine in a control unit to place an erase operation performed on a portion of the memory cells in an erase suspend state based on an erase suspend command decoded by the command decoder, and to place a program operation performed on another portion of the memory cells in a program suspend state if a read command is received while the program operation is performed after the erase operation is suspended; and register circuitry to change a value of a combination of bits stored in the register circuitry from a first value to a second value to indicate that the erase operation and the program operation are concurrently in suspend states, the control unit to ignore an erase suspense command to suspend an in-progress erase operation if the in-progress operation exceeds a finish threshold, and the control unit to ignore a program suspend command if the program suspend command is received while the program operation is performed and while the erase operation is suspended.

7 . The apparatus of claim 6 , wherein the state machine is to exit the program suspend state based on a program resume command decoded by the command decoder.

8 . The apparatus of claim 6 , wherein the state machine is to exit the erase suspend state based on an erase resume command decoded by the command decoder.

9 . The apparatus of claim 6 , wherein the apparatus comprises a flash memory device, and the conductive lines are part of a bus of the flash memory device to provide connections to a memory controller through the conductive lines.

10 . The apparatus of claim 6 , wherein the register circuitry includes a register to store a bit to indicate whether an erase operation is successfully suspended and whether a program operation is successfully suspended.

11 . An apparatus comprising:
an interface; a memory controller coupled to the interface; and a memory device coupled to the controller, the memory device including a control unit, the control unit to suspend an erase operation performed on the memory device based on an erase suspend command and perform a program operation on the memory device, and to suspend the program operation if a read command is received while the program operation is performed and perform a read operation on the memory device while the erase operation and the program operation are suspended, the control unit to ignore an erase suspense command to suspend an in-progress erase operation if the in-progress operation exceeds a finish threshold, and the control unit to ignore a program suspend command if the program suspend command is received while the program operation is performed and while the erase operation is suspended.

12 . The apparatus of claim 11 , wherein the control unit includes a command decoder to decode information received from the memory controller at different times and provide the erase suspend command and the program suspend command.

13 . The apparatus of claim 12 , wherein the command decoder is to decode additional information received from the memory controller and provide a program resume command and an erase resume command order to allow the control unit to resume the program operation based on the program resume command and to resume the erase operation based on the erase resume command.

14 . The apparatus of claim 11 , wherein the interface includes a connector having a form factor complying with one of Peripheral Component Interconnect Express (PCIe) specification, Serial Advanced Technology Attachment (SATA) specification, and Serial Attached Small Computer System Interface (SAS) specification.

15 . The apparatus of claim 11 , wherein the memory controller include a first integrated circuit chip and the memory device includes a second integrated circuit chip.

16 . The apparatus of claim 11 , wherein the interface, the memory controller, and the memory device are included in a solid state drive (SSD).

17 . A method comprising:
performing an erase operation at a memory device; suspending the erase operation; performing a program operation at the memory device while the erase operation is suspended; suspending the program operation if a read command is received while the program operation is performed; performing a read operation at the memory device while the erase operation and the program operation are suspended; ignoring an erase suspense command to suspend an in-progress erase operation if the in-progress operation exceeds a finish threshold; and ignoring a program suspend command if the program suspend command is received while the program operation is performed and while the erase operation is suspended.

18 . The method of claim 17 , further comprising:
receiving an erase command at the memory device, wherein the erase operation is performed in response to the erase command.

19 . The method of claim 17 , further comprising:
receiving a program command at the memory device, wherein the program operation is performed in response to the program command.

20 . The method of claim 17 , further comprising:
receiving a read command at the memory device, wherein the read operation is performed in response to the read command.

21 . The method of claim 17 , further comprising:
resuming the program operation after the read operation is completed.

22 . The method of claim 21 , further comprising:
resuming the erase operation after the program operation is completed.

23 . A method comprising:
providing an erase command to a memory device to cause the memory device to perform an erase operation; providing an erase suspend command to the memory device to cause the memory device to suspend the erase operation; providing a program command to the memory device to cause the memory device to perform a prog

Assignees

• Micron Technology Inc

Inventors

• Madraswala Aliasgar S
• Sule Purval S
• Ramamurthi Karthikeyan

Classifications

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title