Monolithic integration of GaN and InP components

Patent metadata

Field	Value
Publication number	US-9515068-B1
Application number	US-201314014121-A
Country	US
Kind code	B1
Filing date	Aug 29, 2013
Priority date	Aug 29, 2013
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A compound semiconductor integrated circuit comprising a first substrate; a first electronic component formed on top of said first substrate; a layer of a first dielectric material formed on top of said first substrate and including said first electronic component, said layer of a first dielectric material comprising a recess exposing a first region of said first substrate; and a layer of a second dielectric material attached to said first substrate on top of said first region of said first substrate after manufacturing of said layer of a second dielectric material, said layer of a second material comprising a second electronic component.

First claim

What is claimed is:

1. A compound semiconductor integrated circuit comprising:
a first substrate;
a first electronic component formed on top of said first substrate;
a layer of a first dielectric material formed on top of said first substrate and including said first electronic component, said layer of a first dielectric material comprising a recess exposing a first region of said first substrate; at least one first metallic contact being formed in said recess on top of and in contact with at least a portion of said first region; and
a layer of a second dielectric material attached to said first substrate on top of said first region of said first substrate after manufacturing of said layer of a second dielectric material, a second electronic component being at least partly included in said layer of a second dielectric material and at least a portion of said second dielectric material being arranged within said recess; at least one second metallic contact being formed below at least a portion of said layer of a second material; said first and second metallic contacts being formed separately and then connected together.

2. The compound semiconductor integrated circuit of claim 1 , wherein said layer of a first dielectric material and said layer of a second dielectric material have a same thickness and are covered by a third dielectric material layer.

3. The compound semiconductor integrated circuit of claim 1 , comprising an upper electrical connection layer formed above at least portions of said layer of a first dielectric material and said layer of a second dielectric material; said upper electrical connection layer being coupled to the first and second electronic components.

4. The compound semiconductor integrated circuit of claim 1 , wherein each of the first and second electronic components comprises a material combination selected from the group consisting of Group IV-IV, Group III-V and Group II-VI materials.

5. The compound semiconductor integrated circuit of claim 4 , wherein the first electronic component comprises a device selected from the group consisting of a GaN device and an AlGaN device; and wherein the second electronic component comprises a device selected from the group consisting of an InGaAs device, an InAlAs device and an InP device.

6. The compound semiconductor integrated circuit of claim 4 , wherein the first substrate comprises a material selected from the group consisting of Si, InP, GaAs, SiC, Al2O3, GaSb, AlN, InAs and diamond.

7. A compound semiconductor integrated system comprising:
a second substrate;
a third electronic component formed in the second substrate; and
a compound semiconductor integrated circuit as recited in claim 1 attached to said second substrate; at least one of the first and second electronic components being electrically coupled to the third electronic component.

8. The compound semiconductor integrated system of claim 7 , comprising:
a dielectric layer formed on top of said third substrate;
at least a third electrical conductor formed within said dielectric layer;
said compound semiconductor integrated circuit being attached to said dielectric layer.

9. The compound semiconductor integrated circuit of claim 1 , wherein the second electronic component is embedded in the second dielectric material.

10. The compound semiconductor integrated circuit of claim 1 , wherein said first metallic contact is bonded to said second metallic contact using a thermo-compression bonding process.

Assignees

• Hrl Lab Llc

Inventors

• Patterson Pamela R
• Shinohara Keisuke
• Sharifi Hasan
• Ha Wonill
• Hussain Tahir
• Li James Chingwei
• Wheeler Dana C

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W80/334

  Thermocompression bonding · CPC title

• H10W72/01904

  using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title