Reduced threshold voltage-width dependency in transistors comprising high-K metal gate electrode structures

Patent metadata

Field	Value
Publication number	US-9425052-B2
Application number	US-201514698103-A
Country	US
Kind code	B2
Filing date	Apr 28, 2015
Priority date	Aug 31, 2010
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. For example, a carbon species may be incorporated by ion implantation into the active region of a P-channel transistor and an N-channel transistor after selectively forming a threshold adjusted semiconductor material for the P-channel transistor, while the active region of the N-channel transistor is still masked.

First claim

What is claimed:

1. A method, comprising:
performing a first common ion implantation process to implant a carbon species into first and second unmasked active regions of a semiconductor material for a first and a second transistor, respectively;
after performing said first common ion implantation process, forming a masking layer that covers said second active region while leaving said first active region unmasked;
recessing said first active region after performing said first common ion implantation process so as to thereby define a recess in said first active region;
depositing a layer of threshold adjusting semiconductor material in said recess;
with said masking layer in position above said second active region, introducing additional carbon species into said first active region after depositing said layer of threshold adjusting semiconductor material;
forming a first gate electrode structure above said first active region and a second gate electrode structure above said second active region after introducing said additional carbon species, wherein each of said first and second gate electrode structures comprises a gate insulation layer comprising a high-k dielectric material, a portion of said carbon species, said additional carbon species, and said threshold adjusting semiconductor material in said first active region is positioned directly below said high-k dielectric material of said first gate electrode structure, and a portion of said carbon species in said second active region is positioned directly below said high-k dielectric material of said second gate electrode structure; and
forming first drain and source regions of said first transistor in said first active region and second drain and source regions of said second transistor in said second active region.

2. The method of claim 1 , wherein introducing additional carbon species into said first active region comprises, with said masking layer in position above said second active region, performing a second ion implantation process so as to implant said additional carbon species into said first active region.

3. The method of claim 1 , wherein introducing additional carbon species into said first active region comprises, with said masking layer in position above said second active region, introducing said additional carbon species into said threshold adjusting semiconductor material when depositing said layer of threshold adjusting semiconductor material.

4. The method of claim 1 , wherein depositing said layer of threshold adjusting semiconductor material comprises performing an epitaxial growth process to deposit said layer of threshold adjusting semiconductor material.

5. A method, comprising:
forming a first masking layer above a semiconductor material, wherein said first masking layer exposes a first active region in said semiconductor material while covering a second active region in said semiconductor material;
with said first masking layer in position, performing a first ion implantation process to implant a carbon species into said first active region, wherein said carbon species is provided at a first surface region of said first active region;
removing said first masking layer;
forming a second masking layer that exposes said second active region in said semiconductor material while covering said first active region in said semiconductor material;
with said second masking layer in position, performing a second ion implantation process to implant a carbon species into said second active region, wherein said carbon species is provided at a second surface region of said second active region;
removing said second masking layer;
forming a first gate electrode structure above said first active region and a second gate electrode structure above said second active region after removing said second masking layer, wherein each of said first and second gate electrode structures comprises a gate insulation layer comprising a high-k dielectric material, a portion of said carbon species in said first active region is positioned directly below said high-k dielectric material of said first gate electrode structure, and a portion of said carbon species in said second active region is positioned directly below said high-k dielectric material of said second gate electrode structure; and
forming first drain and source regions of a first transistor in said first active region and second drain and source regions of a second transistor in said second active region.

6. The method of claim 5 , wherein said first ion implantation process is performed using a higher implant energy than said second ion implantation process.

7. The method of claim 5 wherein said first ion implantation process is performed with a higher implant dose of said carbon species than said second ion implantation process.

8. The method of claim 5 , wherein said first ion implantation process is performed using a lower implant energy than said second ion implantation process.

9. The method of claim 5 , wherein said first ion implantation process is performed with a lower implant dose of said carbon species than said second ion implantation process.

10. A method, comprising:
performing a first common ion implantation process to implant a carbon species into first and second unmasked active regions of a semiconductor material for a first and a second transistor, respectively;
after performing said first common ion implantation process, forming a masking layer that covers said second active region while leaving said first active region unmasked;
after forming said masking layer, depositing a layer of threshold adjusting semiconductor material in said first active region;
with said masking layer in position above said second active region, performing a second ion implantation process so as to implant additional carbon species into at least said first active region;
forming a first gate electrode structure above said threshold adjusting semiconductor material in said first active region and a second gate electrode structure above said second active region, wherein each of said first and second gate electrode structures comprises a gate insulation layer comprising a high-k dielectric material, a portion of said carbon species and said additional carbon species in said first active region is positioned directly below said high-k dielectric material of said first gate electrode structure, and a portion of said carbon species in said second active region is positioned directly below said high-k dielectric material of said second gate electrode structure; and
forming first drain and source regions of said first transistor in said first active region and second drain and source regions of said second transistor in said second active region.

11. The method of claim 10 , wherein said first common ion implantation process is performed using a lower implant energy than said second ion implantation process.

12. The method of claim 11 , wherein said first common ion implantation process is performed with a lower implant dose of said carbon species than said second ion implantation process.

13. The method of claim 10 , further comprising, with said masking layer in position above said second active region, introducing a carbon species into said threshold adjusting semiconductor material when depositing said layer of threshold adjusting semiconductor material.

14. The method of claim 10 , wherein depositing said layer of threshold adjusting semiconductor material comprises performing an epitaxial growth process to deposit said layer of threshold adjusting semiconductor material.

15. A method, comprising:

Assignees

• Globalfoundries Inc

Inventors

• Scheiper Thilo
• Hoentschel Jan
• Langdon Steven

Classifications

• H10P30/22

  using masks · CPC title

• H10D64/01348

  with substrate doping, e.g. N, Ge or C implantation, before formation of the insulator · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204 Primary

  into Group IV semiconductors · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title