Method for manufacturing high-profile and high-capacitance capacitor

Patent metadata

Field	Value
Publication number	US-11469047-B2
Application number	US-202016810985-A
Country	US
Kind code	B2
Filing date	Mar 6, 2020
Priority date	Mar 6, 2020
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

A method for manufacturing a high-profile capacitor with high capacity includes providing a substrate, forming a first mold layer, a first supporter layer, a second mold layer, and a second supporter layer on the substrate, where at least one of the first mold layer and the second mold layer are made of a dielectric material having a low or super low dielectric constant, defining at least one contact hole, where the now-surrounding first and second supporter layers reinforce the at least one contact hole and form first and second supporter patterns respectively, forming a lower electrode on an inner surface of the at least one contact hole, and removing the first mold layer and/or the second mold layer being made of the dielectric material by ashing.

First claim

What is claimed is:

1. A method for manufacturing a capacitor, the method comprising:
providing a substrate;
forming a first mold layer, a first supporter layer, a second mold layer, and a second supporter layer on the substrate in that order, wherein at least one of the first mold layer and the second mold layer are made of a dielectric material having a low dielectric constant or a super low dielectric constant;
defining at least one contact hole passing through the second supporter layer, the second mold layer, the first supporter layer, and the first mold layer, wherein the first supporter layer and the second supporter layer having the at least one contact hole form a first supporter pattern and a second supporter pattern, respectively;
forming a lower electrode on an inner surface of the at least one contact hole, causing the first supporter pattern and the second supporter pattern to be positioned at a sidewall of the lower electrode; and
removing the first mold layer and the second mold layer, wherein the first mold layer and/or the second mold layer being made of the dielectric material are removed by ashing.

2. The method of claim 1 , wherein the dielectric constant is in a range of 2.0 to 3.0.

3. The method of claim 2 , wherein the dielectric material is a polymer of atom transfer radical polymerization or octamethylcyclotetrasiloxane.

4. The method of claim 1 , wherein the first mold layer is made of boro-phospho-silicate glass, fluosilicate glass, phosphosilicate glass, and any combination thereof, and the second mold layer is made of the dielectric material.

5. The method of claim 4 , wherein the second mold layer is removed by ashing.

6. The method of claim 1 , wherein the first mold layer is made of the dielectric material, and the second mold layer is made of silica.

7. The method of claim 6 , wherein the first mold layer is removed by ashing.

8. The method of claim 1 , wherein both the first mold layer and the second mold layer are made of the dielectric material.

9. The method of claim 8 , wherein both the first mold layer and the second mold layer are removed by ashing.

10. The method of claim 1 , wherein after removing the first mold layer and the second mold layer, the method further comprises:
forming a dielectric layer on the lower electrode having the first supporter pattern and the second supporter pattern; and
forming an upper electrode on the dielectric layer.

11. The method of claim 10 , wherein the dielectric layer is made of hafnium dioxide, aluminum oxide, and any combination thereof.

12. The method of claim 10 , wherein the upper electrode is made of titanium nitride, tungsten nitride, tantalum nitride, copper, aluminum, tungsten, and any combination thereof.

13. The method of claim 1 , wherein the first supporter layer and the second supporter layer are made of silicon nitride.

14. The method of claim 13 , wherein the first supporter layer and the second supporter layer are removed by dry etching or wet etching.

15. The method of claim 1 , wherein the substrate comprises at least one doped region, before forming the first mold layer, the first supporter layer, the second mold layer, and the second supporter layer, the method further comprises:
forming an insulating layer, wherein the insulating layer comprises at least one contact plug passing through the insulating layer, and the at least one contact plug is in contact with one of the at least one doped region.

16. The method of claim 1 , wherein the substrate is made of monocrystalline silicon or silicon-on-insulator.

Assignees

• Xia Tai Xin Semiconductor Qing Dao Ltd

Inventors

• Lee Sang-Man

Classifications

• H01G4/14

  Organic dielectrics · CPC title

• H01G4/224 Primary

  Housing; Encapsulation · CPC title

• H01G4/33

  Thin- or thick-film capacitors {(thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)} · CPC title

• H01G4/008

  Selection of materials · CPC title

• H01G13/06

  with provision for removing metal surfaces · CPC title