Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9659940-B2
Application number	US-201615202874-A
Country	US
Kind code	B2
Filing date	Jul 6, 2016
Priority date	Sep 10, 2015
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A method of manufacturing a semiconductor device includes: preparing a wafer in which a first cell area and a second cell area are defined; forming a bottom electrode structure in the first cell area and a dummy structure located in the second cell area; and sequentially forming a dielectric layer and a top electrode on the bottom electrode structure and the dummy structure, wherein the bottom electrode structure includes a plurality of bottom electrodes extending in a first direction in the first cell area and first and second supporters to support the plurality of bottom electrodes, wherein the dummy structure includes a first mold film, a first supporter film, a second mold film, and a second supporter film that are sequentially formed to cover the second cell area, and the second supporter and the second supporter film are at a same level relative to the wafer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
preparing a wafer in which a chip area having a first cell area and a first peripheral area and an edge area having a second cell area and a second peripheral area are defined;
forming a bottom electrode structure in the first cell area and a dummy structure in the second cell area; and
sequentially forming a dielectric layer and a top electrode on the bottom electrode structure and the dummy structure,
wherein the bottom electrode structure comprises a plurality of bottom electrodes extending in a first direction perpendicular to a top surface of the wafer in the first cell area of the wafer and first and second supporters extending in parallel with the top surface of the wafer to support the plurality of bottom electrodes,
wherein the dummy structure comprises a first mold film, a first supporter film, a second mold film, and a second supporter film that are sequentially formed to cover the second cell area of the wafer, and
the second supporter and the second supporter film are at a same level relative to the wafer.

2. The method of claim 1 , wherein a length of the bottom electrode structure in the first direction is approximately the same as a length of the dummy structure in the first direction.

3. The method of claim 1 , wherein the forming of the bottom electrode structure and the dummy structure comprises:
sequentially forming a first mold layer, a first supporter layer, a second mold layer, and a second supporter layer on the chip area and the edge area;
forming a hole pattern in the first cell area by etching the first mold layer, the first supporter layer, the second mold layer, and the second supporter layer; and
forming a bottom electrode in the hole pattern.

4. The method of claim 3 , wherein the forming of the hole pattern in the first cell area comprises:
forming at least one mask layer on the second supporter layer in the chip area and the edge area;
forming a first preliminary pattern layer on the at least one mask layer in the chip area and the edge area;
forming a first line pattern extending in a second direction in parallel with the top surface of the wafer by patterning the first preliminary pattern layer in the first and second cell areas;
forming a second preliminary pattern layer on the first line pattern in the chip area and the edge area;
forming an etching stopper layer covering the first peripheral area, the second cell area, and the second peripheral area;
forming a second line pattern extending in a third direction crossing the second direction by patterning the second preliminary pattern layer in the first cell area; and
forming a hole pattern mask layer by etching the at least one mask layer in the first cell area by using the first and second line patterns in the first cell area and the etching stopper layer in the first peripheral area, the second cell area, and the second peripheral area as an etching mask.

5. The method of claim 4 , wherein the second supporter in the first cell area and the second supporter film in the second cell area are formed by etching the second supporter layer using the hole pattern mask layer as an etching mask.

6. The method of claim 4 , wherein the etching stopper layer comprises a first etching stopper layer covering the first peripheral area and a second etching stopper layer covering the second cell area and the second peripheral area.

7. A method of manufacturing a semiconductor device, comprising:
preparing a wafer in which a chip area having a first cell area and a first peripheral area and an edge area having a second cell area and a second peripheral area are defined;
sequentially forming a first mold layer, a first supporter layer, a second mold layer, and a second supporter layer on the chip area and the edge area;
forming a plurality of bottom electrodes passing through the first mold layer, the first supporter layer, the second mold layer, and the second supporter layer in the first cell area;
forming a second supporter in the first cell area and a second supporter film in the second cell area by patterning the second supporter layer;
removing the second mold layer from the first cell area, the first peripheral area, and the second peripheral area;
forming a first supporter in the first cell area and a first supporter film in the second cell area by patterning the first supporter layer; and
removing the first mold layer from the first cell area, the first peripheral area, and the second peripheral area.

8. The method of claim 7 , further comprising, between the forming of the plurality of bottom electrodes and the forming of the second supporter and the second supporter film:
exposing the second mold layer by removing the second supporter layer from the first and second peripheral areas;
forming a third mold layer covering the second mold layer in the first and second peripheral areas;
forming a carbon-containing layer and a rework layer sequentially on the second supporter layer in the first and second cell areas and the third mold layer in the first and second peripheral areas;
forming an etching stopper layer covering the rework layer in the edge area; and
forming a supporter mask pattern on the rework layer in the first cell area, wherein the forming of the second supporter is performed by etching the rework layer, the carbon-containing layer, and the second supporter layer by using the supporter mask pattern and the etching stopper layer as an etching mask.

9. The method of claim 8 , wherein a top surface of the second supporter film relative to the wafer comprises a recess portion.

10. The method of claim 7 , further comprising, after the forming of the plurality of bottom electrodes:
forming a first carbon-containing layer and a first rework layer sequentially on the second supporter layer in the chip area and a second carbon-containing layer and a second rework layer sequentially on the second supporter layer in the edge area; and
forming a supporter mask pattern on the first rework layer in the first cell area and the second rework layer in the second cell area,
wherein a top surface of the first carbon-containing layer is at a higher level than a top surface of the second carbon-containing layer relative to the wafer, and
the forming of the second supporter and the second supporter film is performed by etching the second supporter layer by using the supporter mask pattern as an etching mask.

11. The method of claim 10 , wherein the forming of the first carbon-containing layer and the second carbon-containing layer comprises:
forming a carbon-containing layer on the second supporter layer in the chip area and the edge area; and
removing a portion of an upper portion of the carbon-containing layer from the edge area.

12. The method of claim 10 , wherein the supporter mask pattern of the first cell area comprises a plurality of opening portions, and the supporter mask pattern of the second cell area covers the second cell area in its entirety without an opening.

13. The method of claim 12 , wherein the forming of the supporter mask pattern comprises:
forming a supporter mask layer on the first rework layer of the chip area and the second rework layer of the edge area;
forming a blank mask layer covering the supporter mask layer in the chip area;
forming a cell close mask layer covering each of the blank mask layer of the first cell area and the supporter mask layer of the second cell area;
forming a preliminary supporter mask pattern by removing the supporter mask layer of the second peripheral area by using the blank mask layer and the cel

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Hye-Sung
• Hwang In-Seak
• Yoon Bo-Un
• Kwon Byoung-Ho
• Park Jong-Hyuk
• Kim Jae-Hee
• Jang Myung-Jae

Classifications

• H01L27/10852 Primary

  Electricity · mapped topic

• H01L27/10897

  Electricity · mapped topic

• H01L27/10814

  Electricity · mapped topic

• H10D1/716 Primary

  having vertical extensions · CPC title

• H10B12/50

  Peripheral circuit region structures · CPC title