Memory device capable of operation in wide temperature range and data processing system and method of operating the same

Patent metadata

Field	Value
Publication number	US-9786336-B2
Application number	US-201514801860-A
Country	US
Kind code	B2
Filing date	Jul 17, 2015
Priority date	Sep 12, 2014
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A data processing system includes a first memory, a second memory, a temperature sensor, and a controller. The temperature sensor is configured to sense a temperature at the data processing system and generate a temperature signal. The controller is configured to control whether the first memory is enabled or disabled and whether the second memory is enabled or disabled based on the temperature signal and based on a first temperature threshold associated with the first memory and a second temperature threshold associated with the second memory.

First claim

What is claimed is:

1. A method of controlling a memory device in a data processing system, the memory device including at least a first memory chip and a second memory chip, the method comprising:
generating a temperature signal that reflects a temperature at the data processing system;
based on the temperature signal, determining if the temperature at the data processing system is lower than a low temperature threshold;
based on the temperature signal, determining if the temperature at the data processing system is higher than a high temperature threshold;
when it is determined that the temperature at the data processing system is lower than the low temperature threshold, enabling the second memory chip and disabling the first memory chip; and
when it is determined that the temperature at the data processing system is higher than the high temperature threshold, enabling the first memory chip and disabling the second memory chip,
wherein the high temperature threshold has a higher temperature value than the low temperature threshold.

2. The method of claim 1 , further comprising:
when it is determined that the temperature at the data processing system is higher than the low temperature threshold and lower than the high temperature threshold, enabling both the first memory chip and the second memory chip.

3. The method of claim 2 , further comprising:
when it is determined that the temperature at the data processing system is higher than the low temperature threshold and lower than the high temperature threshold, copying data from one of the first memory chip or second memory chip to the other of the first memory chip or second memory chip.

4. The method of claim 3 , further comprising:
copying data from the second memory chip to the first memory chip when a temperature passes and increases above the low temperature threshold, and
copying data from the first memory chip to the second memory chip when a temperature passes and decreases below the high temperature threshold.

5. The method of claim 1 , wherein the temperature signal reflects an ambient temperature at the memory device.

6. The method of claim 1 , further comprising:
controlling the first memory chip to operate within a first range of temperatures; and
controlling the second memory chip to operate within a second range of temperatures,
wherein the first range of temperatures is higher than the second range of temperatures, and the first range of temperatures overlaps the second range of temperatures.

7. The method of claim 6 , wherein:
the first memory chip operates most efficiently in the first range of temperatures; and
the second memory chip operates most efficiently in the second range of temperatures.

8. The method of claim 1 , wherein the first memory chip is part of a first semiconductor package of the memory device, and the second memory chip is part of a second semiconductor package of the memory device.

9. The method of claim 1 , wherein the enabling/disabling of the first and second memory chips is accomplished using a chip enable signal.

10. A data processing system comprising:
a first memory;
a second memory;
a temperature sensor configured to sense a temperature at the data processing system and generate a temperature signal; and
a controller,
wherein the controller is configured to control whether the first memory is enabled or disabled based on the temperature signal and a first temperature threshold associated with the first memory, and to control whether the second memory is enabled or disabled based on the temperature signal and a second temperature threshold associated with the second memory, wherein the second temperature threshold is lower than the first temperature threshold.

11. The data processing system of claim 10 , wherein the controller is configured to enable only the first memory from among the first memory and second memory when the sensed temperature is higher than the first temperature threshold, and enable only the second memory from among the first memory and second memory when the sensed temperature is lower than the second temperature threshold.

12. The data processing system of claim 11 , wherein the controller is configured to enable the first memory and the second memory when the sensed temperature is higher than the second temperature threshold and is lower than the first temperature threshold.

13. The data processing system of claim 11 , wherein the controller is configured to enable the second memory and copy data stored in the first memory into the enabled second memory when the sensed temperature becomes lower than the first temperature threshold, and to disable the first memory when the sensed temperature becomes lower than the second temperature threshold.

14. The data processing system of claim 11 , wherein the controller is configured to enable the first memory and copy data stored in the second memory into the enabled first memory when the sensed temperature becomes higher than the second temperature threshold, and disable the second memory when the sensed temperature becomes higher than the first temperature threshold.

15. The data processing system of claim 10 , wherein the first memory and the second memory are first and second respective memory chips packaged into one package.

16. The data processing system of claim 10 , wherein the first memory and the second memory are first and second respective memory chips attached to one memory module.

17. The data processing system of claim 10 , wherein the first and second memories are part of a memory device connected to the controller through an interface, and the temperature sensor is located at one of the controller or the memory device.

18. A controller for controlling a memory device including a first memory chip and a second memory chip, the controller configured to:
determine whether a sensed temperature at one of the controller or the memory device is higher than a first threshold temperature;
determine whether the sensed temperature is lower than a second threshold temperature;
enable the first memory chip and disable the second memory chip when the sensed temperature is higher than the first threshold temperature; and
enable the second memory chip and disable the first memory chip when the sensed temperature is lower than the second threshold temperature,
wherein the second threshold temperature is lower than the first threshold temperature.

19. The controller of claim 18 , wherein the controller is further configured to:
enable both the first memory chip and the second memory chip when the sensed temperature is higher than the second threshold temperature, and is lower than the first threshold temperature.

20. The controller of claim 19 , wherein the controller is further configured to:
when the sensed temperature is lower than the first threshold temperature and higher than the second threshold temperature, copy data from one of the first memory chip and the second memory chip to the other of the first memory chip and the second memory chip.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Woo Mi Young
• Ha Kae Won
• Kim Myong Jae

Classifications

• G11C11/40626

  Temperature related aspects of refresh operations · CPC title

• G11C7/04 Primary

  with means for avoiding disturbances due to temperature effects · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F3/065

  Replication mechanisms · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title