Memory with per die temperature-compensated refresh control

Patent metadata

Field	Value
Publication number	US-11200939-B1
Application number	US-202016921729-A
Country	US
Kind code	B1
Filing date	Jul 6, 2020
Priority date	Jul 6, 2020
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

Memory devices, systems, and associated methods with per die temperature-compensated refresh control, and associated methods, are disclosed herein. In one embodiment, a memory device includes a plurality of memory cells and a sensor configured to measure a temperature of the memory device. The memory device determines a frequency at which it is receiving refresh commands. The memory device is further configured to skip refresh operations of the memory cells based, at least in part, on the determination and on the temperature of the memory device.

First claim

What is claimed is:

1. A memory device, comprising:
a plurality of memory cells; and
a sensor configured to measure a temperature of the memory device,
wherein the memory device is configured to:
determine, based at least in part on a notification received by the memory device, a frequency at which refresh commands are being received by the memory device, wherein the notification is received in at least one address bit of an address signal received at an external pin of the memory device; and
skip refresh operations of the memory cells based at least in part on the determination and on the temperature of the memory device.

2. The memory device of claim 1 , wherein the memory device is configured to:
skip a first number of refresh operations when the temperature is below a threshold temperature value; and
skip a second number of refresh operations when the temperature is at or above the threshold temperature value.

3. The memory device of claim 2 , wherein the first number corresponds to skipping every other refresh operation.

4. The memory device of claim 2 , wherein the second number is zero.

5. The memory device of claim 2 , wherein the threshold temperature value is equal to or greater than 70° C.

6. The memory device of claim 2 , wherein:
the threshold temperature value is a first threshold temperature value;
the memory device is further configured to skip a third number of refresh operations when the temperature is below a second threshold temperature value;
the second threshold temperature value is less than the first threshold temperature value; and
the third number is greater than the first number.

7. The memory device of claim 6 , wherein the second threshold temperature value is between 45° C. and 60° C.

8. The memory device of claim 1 , wherein the memory device is configured to skip every third refresh operation when the temperature is below a threshold temperature value.

9. The memory device of claim 1 , wherein the notification indicates a refresh scheme of a memory controller.

10. The memory device of claim 1 , wherein the memory device is configured to receive the address signal when the memory device registers a refresh command.

11. The memory device of claim 1 , wherein, to skip refresh operations, the memory device is further configured to:
receive one or more refresh commands instructing the memory device to execute one or more refresh operations; and
in response to receiving the one or more refresh commands, refrain from executing at least a subset of the one or more refresh operations.

12. The memory device of claim 1 , wherein the memory device is an individual dynamic random-access memory (DRAM) memory die.

13. A method, comprising:
receiving, at one or more external pins of a memory device, a notification in at least one address bit of an address signal, wherein the notification indicates a frequency at which refresh commands are being received by the memory device, and wherein the memory device is one of a plurality of memory devices of a dual in-line memory module (DIMM);
determining a temperature of the memory device; and
skipping refresh operations of memory cells of the memory device based, at least in part, on the notification and on the temperature of the memory device.

14. The method of claim 13 , wherein the skipping includes skipping a number of refresh operations when the temperature is below a threshold temperature value.

15. The method of claim 14 , wherein the number corresponds to skipping every other or every third refresh operation.

16. The method of claim 14 , wherein the number is a first number, and wherein the skipping includes skipping a second number of refresh operations when the temperature is at or above the threshold temperature value.

17. The method of claim 16 , wherein the second number of refresh operations is zero.

18. The method of claim 14 , wherein:
the threshold temperature value is a first threshold temperature value;
the number of refresh operations is a first number of refresh operations;
the method further comprises skipping a second number of refresh operations when the temperature is below a second threshold temperature value;
the second threshold temperature value is less than the first threshold temperature value; and
the second number is greater than the first number.

19. The method of claim 13 , wherein:
receiving the notification includes receiving the address signal when the memory device registers a refresh command;
the notification indicates a refresh mode that specifies the frequency at which the memory device is receiving the refresh commands; and
the method further comprises determining the refresh mode by monitoring the at least one address bit of the address signal.

20. The method of claim 13 , wherein determining the temperature includes determining the temperature of the memory device using a sensor internal to the memory device.

21. The method of claim 13 , wherein skipping the refresh operations includes:
receiving one or more refresh commands instructing the memory device to execute one or more refresh operations; and
in response to receiving the one or more refresh commands, refraining from executing at least a subset of the one or more refresh operations.

22. A memory system, comprising:
a memory controller; and
a memory device including—
a plurality of memory cells; and
a sensor configured to measure a temperature of the memory device; and
an external pin configured to receive address signals,

wherein the memory device is configured to:
receive an address signal from the memory controller at the external pin, wherein the address signal includes a notification in at least one address bit of the address signal, and wherein the notification indicates a frequency at which the memory controller is issuing refresh commands; and
skip refresh operations of the memory cells based; at least in part on the notification and on the temperature of the memory device.

23. The memory system of claim 22 , wherein the memory device is configured to determine a refresh mode of the memory controller by monitoring the at least one address bit of the address signal, wherein the refresh mode specifies the frequency, and wherein the address signal is received by the memory device when the memory device registers a refresh command.

24. The memory system of claim 22 , wherein the memory device is configured to:
skip a first number of refresh operations when the temperature is at or above a first threshold temperature value;
skip a second number of refresh operations when the temperature is below the first threshold temperature value; and
skip a third number of refresh operations when the temperature is below a second threshold temperature value, the second threshold temperature value being less than the first threshold temperature value.

25. The memory system of claim 22 , wherein:
the memory device is further configured to send an indication of the temperature to the memory controller; and
the memory controller is configured to increase the frequency based, at least in part, on the temperature.

Assignees

• Micron Technology Inc

Inventors

• Rehmeyer James S
• Johnson Jason M
• Lee Joo-Sang

Classifications

• G06F11/3037

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title

• G06F11/3058

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title

• G11C11/40626 Primary

  Temperature related aspects of refresh operations · CPC title

• G11C11/40622

  Partial refresh of memory arrays · CPC title

• G11C11/40607

  Refresh operations in memory devices with an internal cache or data buffer · CPC title