Semiconductor device including a spacer in contact with an upper surface of a silicide layer

Patent metadata

Field	Value
Publication number	US-11468919-B2
Application number	US-202016841850-A
Country	US
Kind code	B2
Filing date	Apr 7, 2020
Priority date	Jul 29, 2019
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate a bit line structure disposed on the substrate, a trench adjacent to at least one side of the bit line structure, a storage contact structure disposed within the trench, and comprising a storage contact, a silicide layer, and a storage pad which are stacked sequentially. A spacer structure is disposed between the bit line structure and the storage contact structure.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a bit line structure disposed on the substrate;
a trench adjacent to at least one side of the bit line structure;
a storage contact structure disposed within the trench, and comprising a storage contact, a silicide layer, and a storage pad; and
a spacer structure disposed between the bit line structure and the storage contact structure,
wherein the spacer structure comprises:
a first spacer in contact with a sidewall of the bit line structure; and
a second spacer disposed on the first spacer, the second spacer in contact with a sidewall of the storage pad, the second spacer includes an insulating material, and
wherein a lower surface of the second spacer is in contact with an upper surface of the silicide layer.

2. The semiconductor device of claim 1 , further comprising:
a bit line contact disposed on the substrate,
wherein an upper surface of the storage contact is disposed below an upper surface of the contact.

3. The semiconductor device of claim 2 , further comprising a third spacer disposed between the first spacer and the second spacer.

4. The semiconductor device of claim 3 , further comprising a fourth spacer disposed between the third spacer and the second spacer.

5. The semiconductor device of claim 4 , wherein the third spacer is an air spacer.

6. The semiconductor device of claim 3 , wherein the hit line structure comprises a bit line and a capping pattern disposed on the bit line,
wherein a lower Sidewall of the capping pattern is in contact with the first spacer, and
wherein an upper sidewall of the capping pattern is in contact with the storage pad.

7. The semiconductor device of claim 2 , wherein the second spacer comprises:
a fifth spacer in contact with the sidewall of the storage pad; and
a sixth spacer disposed between the first spacer and the fifth spacer.

8. The semiconductor device of claim 7 , wherein a lower surface of the fifth spacer and a lower surface of the sixth spacer are in contact with the upper surface of the silicide layer.

9. The semiconductor device of claim 1 , wherein a first thickness of the spacer structure in contact with a sidewall of the storage pad is larger than second thickness of the spacer structure in contact with a sidewall of the storage contact.

10. The semiconductor device of claim 1 , further comprising a capacitor disposed on the storage contact structure and electrically connected with the storage pad.

11. A semiconductor device, comprising
a substrate;
a bit line contact disposed on the substrate;
a bit line structure disposed on the bit line Contact;
a trench adjacent to at least one side of the bit line structure;
a storage contact structure disposed within the trench, and comprising a storage contact, a silicide layer, and a storage pad which are stacked sequentially;
a first spacer in contact with a sidewall of the bit line structure; and
a second spacer disposed on the first spacer, the second spacer in contact with a sidewall of the storage pad and an upper surface of the silicide layer, the second spacer includes an insulating material.

12. The semiconductor device of claim 11 , wherein an upper surface of the storage contact is lower than an upper surface of the bit line contact.

13. The semiconductor device of claim 11 , wherein the bit line structure comprises a bit line and a capping pattern disposed on the bit line, and
wherein the upper surface of the silicide layer is higher than an upper surface of the bit line.

14. The semiconductor device of claim 11 , wherein the storage contact comprises:
a first lower surface in contact with an isolation layer within the substrate; and
a second lower surface in contact with an active region defined by the isolation layer,
wherein the first lower surface is higher than the second lower surface.

15. The semiconductor device of claim 11 , further comprising:
a third spacer disposed between the first spacer and the second spacer; and
a fourth spacer disposed between the third spacer and the second spacer.

16. The semiconductor device of claim 11 , wherein the second spacer comprises:
a fifth spacer in contact with the sidewall of the storage pad; and
a sixth spacer disposed between the first spacer and the fifth spacer.

17. A semiconductor device, comprising:
a substrate comprising an isolation layer and an active region adjacent to the isolation layer;
a bit line contact disposed on the substrate;
a bit line structure disposed on the bit line contact;
a trench adjacent to at least one side of the bit line structure;
a storage contact structure disposed within the trench, and comprising a storage contact, a suicide layer, and a storage pad which are stacked sequentially;
first, second, third and fourth spacers disposed between the bit line structure and the storage contact structure, wherein the first, second, third and fourth spacers are stacked sequentially on a sidewall of the bit line structure; and
a capacitor disposed on the storage contact structure and electrically connected with the storage pad,
wherein an upper surface of the storage contact is lower than an upper surface of the bit line contact, and
wherein a lower surface of the fourth spacer is in contact with an upper surface of the suicide laver, the fourth spacer includes an insulating material.

18. The semiconductor device of claim 17 , wherein the bit line structure comprises a line and a capping pattern disposed on the bit line, and
wherein the upper surface of the silicide layer is lower than an upper surface of the bit line.

19. The semiconductor device of claim 17 , wherein the fourth spacer comprises:
a fifth spacer disposed on the third spacer and having a lower surface in contact with the upper surface of the silicide laver, and
a sixth spacer disposed on the fifth spacer.

20. The semiconductor device of claim 17 , wherein the second spacer is air spacer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Tae Jin
• Yoo Won Seok
• Kim Keun Nam
• Kim Hyo-Sub
• Park So Hyun
• Heo In Kyoung
• Hwang Yoo Sang

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• H01L27/10855

  Electricity · mapped topic

• H01L27/10823

  Electricity · mapped topic

• H01L27/10876

  Electricity · mapped topic