Semiconductor device including buried contact and method for manufacturing the same
US-12178034-B2 · Dec 24, 2024 · US
Semiconductor devices
US9099343B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9099343-B2 |
| Application number | US-201314057530-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 18, 2013 |
| Priority date | Oct 18, 2012 |
| Publication date | Aug 4, 2015 |
| Grant date | Aug 4, 2015 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
Provided are semiconductor devices and methods of fabricating the same. In methods of forming the same, an etch stop pattern and a separate spacer can be formed on a sidewall of a bit line contact, wherein the etch stop pattern and the separate spacer each comprise material having an etch selectivity relative to an oxide. A storage node contact plug hole can be formed so that the etch stop pattern and the separate spacer form a portion of a sidewall of the storage node contact plug hole spaced apart from the bit line contact. The storage node contact plug hole can be cleaned to remove a natural oxide formed in the storage node contact plug hole. Related devices are also disclosed.
First claim
Opening claim text (preview).
What is claimed: 1. A semiconductor device, comprising: a substrate; a first doped region and a second doped region provided spaced apart from each other on the substrate; a storage node contact plug in contact with the first doped region; a bitline electrically connected to the second doped region; a bitline node contact plug disposed between the bit line and the second doped region; and a spacer interposed between the bit line and the storage node contact plug and bet…
Assignees
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10W20/069Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9099343B2 cover?
- Provided are semiconductor devices and methods of fabricating the same. In methods of forming the same, an etch stop pattern and a separate spacer can be formed on a sidewall of a bit line contact, wherein the etch stop pattern and the separate spacer each comprise material having an etch selectivity relative to an oxide. A storage node contact plug hole can be formed so that the etch stop patt…
- Who is the assignee on this patent?
- Kim Keunnam, Park Sunyoung, Yeom Kyehee, and 5 more
- What technology area does this patent fall under?
- Primary CPC classification H10W20/069. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Aug 04 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).