Methods of manufacturing semiconductor devices including air gap spacers

Patent metadata

Field	Value
Publication number	US-9318379-B2
Application number	US-201514939439-A
Country	US
Kind code	B2
Filing date	Nov 12, 2015
Priority date	Aug 30, 2013
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

A spacer covering a sidewall of a contact plug includes a relatively more damaged first portion and a relatively less damaged second portion. An interface of the first and second portions of the spacer is spaced apart from a metal silicide layer of the contact plug. Thus reliability of the semiconductor device may be improved. Related fabrication methods are also described.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming line patterns on a substrate;
forming a sacrificial spacer and a first spacer that sequentially are on a sidewall of each of the line patterns;
forming a poly-silicon layer in a space between line patterns;
performing a first etching process on the poly-silicon layer to form a first-etched poly-silicon layer in the space between the line patterns and to expose a first portion of the first spacer, the first spacer further including a second portion not exposed under the first portion;
performing a second etching process on the first-etched poly-silicon layer to form a poly-silicon pattern between the line patterns; and
forming a metal silicide layer on a top surface of the poly-silicon pattern,
wherein the metal silicide layer is formed to be spaced apart from an interface between the first portion and the second portion of the first spacer.

2. The method of claim 1 , wherein the first etching process is an anisotropic etching process and the second etching process is an isotropic etching process, and
wherein a sidewall of the second portion is partially exposed by the second etching process.

3. The method of claim 1 , further comprising:
forming a second spacer on the first portion before performing the second etching process.

4. The method of claim 3 , wherein the second etching process is an anisotropic etching process,
wherein the second etching process is performed using the second spacer as an etch mask, and
wherein the poly-silicon pattern is formed on a sidewall of the second portion.

5. The method of claim 4 , wherein a recess region is formed in a top surface of the poly-silicon pattern, which is not covered by the second spacer,
the method further comprising:
forming a third spacer on a sidewall of the second spacer and an inner sidewall of the recess region before the formation of the metal silicide layer.

6. The method of claim 5 , further comprising:
removing the third spacer after the formation of the metal silicide layer.

7. The method of claim 1 , further comprising:
forming a second spacer on the sidewall of each of the line patterns before the formation of the sacrificial spacer.

8. The method of claim 1 , wherein a height difference between the interface and a top surface of the metal silicide layer is in the range of about 50 Å to about 500 Å.

9. The method of claim 1 , further comprising:
forming a metal-containing layer in the space between the line patterns; and
removing the sacrificial spacer to form an air gap.

10. The method of claim 9 , wherein the metal-containing layer is formed on the line patterns,
the method further comprising:
etching the metal-containing layer to form a landing pad and to expose a top end of the sacrificial spacer before removing the sacrificial spacer.

11. The method of claim 10 , wherein each of the line patterns includes an interconnection pattern and a hardmask pattern which are sequentially stacked,
wherein a height difference between a top surface of the hardmask pattern and a top surface of the first spacer is in the range of about 0 Å to about 500 Å.

12. A method of manufacturing a semiconductor device, the method comprising:
forming a region on a substrate, the region including a sidewall;
forming a first spacer extending on the sidewall, the first spacer including a sacrificial layer having a first end adjacent the substrate and a second end remote from the substrate;
forming a contact on the first spacer, the contact having a first end adjacent the substrate and a second end that is between the first and second ends of the first spacer;
forming a second spacer extending on the first spacer, the second spacer having a second end that is adjacent the second end of the first spacer and a first end that is adjacent the second end of the contact;
recessing the second end of the contact so that it is spaced farther apart from the first end of the second spacer; and
removing the sacrificial layer to create an air gap in the first spacer, the air gap having a first end adjacent the substrate and a second end remote from the substrate.

13. The method of claim 12 wherein the following is performed between the recessing and the removing:
forming a metal silicide layer that extends on the second end of the contact.

14. The method of claim 13 wherein the metal silicide layer is spaced apart from the air gap throughout an extent of the metal silicide layer.

Assignees

• Lee Eun-Ok
• Kim Nam-Gun
• Oh Gyuhwan
• Park Heesook
• Lee Hyun-Jung
• Jang Kyungho
• Samsung Electronics Co Ltd

Inventors

• Lee Eun-Ok
• Kim Nam-Gun
• Oh Gyuhwan
• Park Heesook
• Lee Hyun-Jung
• Jang Kyungho

Classifications

• H10W20/4403 Primary

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/066

  by forming silicides of refractory metals · CPC title