Array substrate, display panel and display apparatus

Patent metadata

Field	Value
Publication number	US-11467456-B2
Application number	US-201916963531-A
Country	US
Kind code	B2
Filing date	Dec 17, 2019
Priority date	Jan 17, 2019
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

Embodiments of the present disclosure provide an array substrate, a display panel, and a display apparatus. The array substrate includes: a display region for displaying an image; a non-display region; a shift register provided in the non-display region; a gate line provided in the display region and extending along a first direction; and a gate signal output line, provided in the non-display region and having a first end and a second end. The first end of the gate signal output line is connected to the shift register, and the second end of the gate signal output line is connected to the gate line at a side of the gate line in a second direction perpendicular to the first direction.

First claim

What is claimed is:

1. An array substrate, comprising:
a display region for displaying an image;
a non-display region;
a shift register provided in the non-display region;
a gate line provided in the display region and extending along a first direction;
a gate signal output line, provided in the non-display region and having a first end and a second end, the first end of the gate signal output line being connected to the shift register, and the second end of the gate signal output line being connected to the gate line at a side of the gate line in a second direction perpendicular to the first direction;
a common electrode leading wire, provided in a same layer as the gate line, and extending in a direction crossing the gate line;
a gate insulating layer covering the common electrode leading wire and the gate line, the gate signal output line being provided on the gate insulating layer; and
a jumper pad, comprising a first connection sheet and a second connection sheet, wherein
the first connection sheet extends along the second direction, and the second connection sheet extends along the second direction;
the first connection sheet and the second connection sheet are respectively arranged on opposite sides of the gate insulating layer;
the first connection sheet is connected to and provided in a same layer as the gate line, and the second connection sheet is connected to and provided in a same layer as the gate signal output line, and the first connection sheet and the second connection sheet are connected through a via hole formed in the gate insulating layer; and

the second end of the gate signal output line is connected to the jumper pad at a side of the jumper pad in the second direction, and the gate line is connected to the jumper pad at a side of the jumper pad away from the non-display region in the first direction.

2. The array substrate according to claim 1 , wherein:
the gate signal output line comprises a lead-out section and a transfer section, and each of the lead-out section and the transfer section comprises a first end and a second end, and the first end of the lead-out section is connected to the shift register, the second end of the lead-out section is connected to the first end of the transfer section, the second end of the transfer section is connected to the gate line through the jumper pad, and an angle between the transfer section and the gate line is within a range of 45° to 90°.

3. The array substrate according to claim 2 ,
wherein the non-display region comprises a circuit region and a transfer region, the transfer region is located between the display region and the circuit region, the transfer section of the gate signal output line and the jumper pad are located in the transfer region, and the common electrode leading wire is provided in the transfer region.

4. The array substrate according to claim 2 , wherein:
the gate signal output line further comprises an intermediate section, a first end of the intermediate section is connected to the second end of the lead-out section, a second end of the intermediate section is connected to the first end of the transfer section, and an angle between the intermediate section and the transfer section is within a range of 30° to 60°.

5. The array substrate according to claim 4 , wherein:
the intermediate section has a straight-line shape or an arc shape.

6. The array substrate according to claim 1 , further comprising:
a data line, provided in a same layer as the gate signal output line.

7. The array substrate according to claim 1 , wherein:
the jumper pad is located on a side of the common electrode leading wire facing the gate line in the first direction.

8. The array substrate of claim 7 , wherein:
the second end of the gate signal output line is connected to the second connection sheet of the jumper pad at a side of the second connection sheet of the jumper pad in the second direction, and the gate line is connected to the first connection sheet of the jumper pad at a side of the first connection sheet of the jumper pad away from the non-display region in the first direction.

9. The array substrate of claim 7 , wherein:
the gate signal output line comprises a lead-out section and a transfer section, each of the lead-out section and the transfer section comprises a first end and a second end, and the first end of the lead-out section is connected to the shift register, the second end of the lead-out section is connected to the first end of the transfer section, the second end of the transfer section is connected to the gate line through the jumper pad, and an angle between the transfer section and the gate line is within a range of 45° to 90°, and
in a direction parallel to the common electrode leading wire, a distance between an edge of the second connection sheet facing the lead-out section and an edge of the lead-out section facing the second connection sheet is greater than 18 μm.

10. The array substrate according to claim 1 , further comprising:
a connection line, provided in the non-display region and having a first end and a second end, wherein the first end of the connection line is connected to the gate line at a side of the gate line in the second direction perpendicular to the first direction, and the second end of the connection line is connected to the gate signal output line.

11. The array substrate according to claim 10 , further comprising:
a jumper pad, wherein the second end of the gate signal output line and the second end of the connection line are respectively at opposite first and second sides of the jumper pad in the second direction, and connected to each other through the jumper pad.

12. The array substrate according to claim 10 , further comprising:
a common electrode leading wire, provided in a same layer as the gate line, and extending in a direction crossing the gate line;
a gate insulating layer covering the common electrode leading wire and the gate line, wherein the gate signal output line is provided on the gate insulating layer; and
a jumper pad, comprising a first connection sheet and a second connection sheet, wherein the first connection sheet and the second connection sheet are connected through a via hole formed in the gate insulating layer, the second end of the gate signal output line is connected to the second connection sheet at a first side of the jumper pad in the second direction and the second connection sheet is provided in a same layer as the gate signal output line, and the second end of the connection line is connected to the first connection sheet at a second side, opposite to the first side, of the jumper pad in the second direction and the first connection sheet is provided in a same layer as the connection line and the gate line.

13. The array substrate of claim 12 , wherein:
the connection line comprises a first connection line portion and a second connection line portion, a first end of the second connection line portion of the connection line is connected to the gate line, and a second end of the second connection line portion of the connection line is connected to a first end of the first connection line portion of the connection line, and a second end of the first connection line portion of the connection line is connected to the first connection sheet of the jumper pad.

14. The array substrate of claim 13 , wherein:
the second connection line portion of the connection line has a straight-line shape, and an angle between the second connection line portion of the connection line and the first connection line portion is within a range of 30° to 60°, or the first connection

Assignees

• Chongqing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Zhang Pengyue
• Liu Zhulin
• Wang Xiaolin
• Park Jungho
• Xu Zhuo

Classifications

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G02F1/134309

  characterised by their geometrical arrangement · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G09G2330/04

  Display protection · CPC title