Display driver and display device

US9640130B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9640130-B2
Application numberUS-201414470971-A
CountryUS
Kind codeB2
Filing dateAug 28, 2014
Priority dateAug 28, 2013
Publication dateMay 2, 2017
Grant dateMay 2, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display driver is connectable with and serves to activate an active matrix type display panel having a plurality of source lines wired to run in an up-and-down direction and a plurality of gate lines wired to run in left and right directions when viewed from a direction perpendicular to a substrate, and a plurality of pixels respectively arranged at intersections where the source and gate lines intersect with one another; electric charges corresponding to display data are transmitted from the source lines to the pixels selected by the driven gate line. The display driver includes a circuit capable of adjusting, in amplitude, first gate drive circuits operable to drive, of the plurality of gate lines, gate lines wired from the left, and second gate drive circuits operable to drive gate lines wired from the right independently of one another.

First claim

Opening claim text (preview).

What is claimed is: 1. A display driver connectable with a display panel having a plurality of source lines wired to run in an up-and-down direction and a plurality of gate lines wired to run in left and right directions when viewed from a direction perpendicular to a substrate, and a plurality of pixels respectively arranged at intersections where the source and gate lines intersect with one another, in which electric charges corresponding to display data are transmitted from the source lines to the pixels selected by the driven gate line, the display driver comprising: an output-amplitude-adjustment circuit capable of adjusting, in output amplitude, a group of first gate drive circuits operable to drive, of the plurality of gate lines, a group of first gate lines wired from the left, and a group of second gate drive circuits operable to drive a group of second gate lines wired from the right, wherein the output-amplitude-adjustment circuit adjusts said first and second gate line groups independently of one another, and wherein the output-amplitude-adjustment circuit comprises a first register which determines a first maximum amplitude among amplitudes driven by the first gate drive circuits, and a second register which determines a second maximum amplitude among amplitudes driven by the second gate drive circuits, so as to decrease differences between first maximum amplitudes on the first gate lines which are controlled by setting a first value in the first register, and second maximum amplitudes on the second gate lines which are controlled by setting a second value in the second register. 2. The display driver according to claim 1 , wherein the output-amplitude-adjustment circuit makes the output amplitude of the first gate drive circuit longer in wiring length to the first gate line to be driven in the group of first gate drive circuits larger than that of the first gate drive circuit shorter in wiring length to the first gate line to be driven, and the output-amplitude-adjustment circuit makes the output amplitude of the second gate drive circuit longer in wiring length to the second gate line to be driven in the group of second gate drive circuits larger than that of the second gate drive circuit shorter in wiring length to the second gate line to be driven. 3. The display driver according to claim 2 , wherein the output-amplitude-adjustment circuit is capable of adjusting, based on the wiring length to the first gate line to be driven, the output amplitude of first gate drive circuits included in each of sub-groups which the group of first gate drive circuits are divided into to have a value based on the wiring length, and the output-amplitude-adjustment circuit is capable of adjusting, based on the wiring length to the second gate line to be driven, the output amplitude of second gate drive circuits included in each of sub-groups which the group of second gate drive circuits are divided into to have a value based on the wiring length. 4. The display driver according to claim 2 , wherein the output-amplitude-adjustment circuit is capable of successively adjusting the output amplitude of a first gate drive circuit included in the group of first gate drive circuits based on the wiring length to the first gate line to be driven, and the output-amplitude-adjustment circuit is capable of successively adjusting the output amplitude of a second gate drive circuit included in the group of second gate drive circuits based on the wiring length to the second gate line to be driven. 5. The display driver according to claim 1 , wherein the group of first gate drive circuits and the group of second gate drive circuits are mounted on the display panel, the display driver supplies the group of first gate drive circuits with a first power source, and the group of second gate drive circuits with a second power source, and the output-amplitude-adjustment circuit is capable of adjusting, in voltage, the first power source and the second power source independently of each other. 6. The display driver according to claim 5 , wherein the output-amplitude-adjustment circuit is capable of adjusting the voltage of the first power source when a first gate line farther from the display driver is driven to be higher than the voltage of the first power source when a first gate line closer to the display driver is driven, and the output-amplitude-adjustment circuit is capable of adjusting the voltage of the second power source when a second gate line farther from the display driver is driven to be higher than the voltage of the second power source when a second gate line closer to the display driver is driven. 7. The display driver according to claim 1 , wherein the display panel further includes a touch panel laminated on the substrate and having a plurality of touch detection lines, the display driver further comprises a plurality of receive circuits connected with the plurality of touch detection lines respectively, and each capable of detecting the amplitude of a signal on the corresponding touch detection line, and the output-amplitude-adjustment circuit is capable of adjusting the output amplitude of at least one of the group of first gate drive circuits and the group of second gate drive circuits to make smaller differences between amplitude values of signals detected by the plurality of receive circuits when the group of first gate lines are driven by the group of first gate drive circuits, and amplitude values of signals detected by the plurality of receive circuits when the group of second gate lines are driven by the group of second gate drive circuits. 8. The display driver according to claim 7 , wherein the output-amplitude-adjustment circuit is capable of adjusting the output amplitude of a first gate drive circuit included in the group of first gate drive circuits to make smaller differences between signal amplitudes detected by the receive circuits when a first gate line farther from the display driver is driven, and signal amplitudes detected by the receive circuits when a first gate line closer to the display driver is driven, and the output-amplitude-adjustment circuit is capable of adjusting the output amplitude of a second gate drive circuit included in the group of second gate drive circuits so as to make smaller differences between signal amplitudes detected by the receive circuits when a second gate line farther from the display driver is driven, and signal amplitudes detected by the receive circuits when a second gate line closer to the display driver is driven. 9. The display driver according to claim 7 , wherein the plurality of touch detection lines include a group of first touch detection lines wired in an up-and-down direction, and groups of second touch detection lines wired in left and right directions, and the output-amplitude-adjustment circuit is capable of adjusting the output amplitude of at least one of the group of first gate drive circuits and the group of second gate drive circuits to make smaller differences between amplitude values of signals detected by receive circuits connected with the groups of second touch detection lines when the group of first gate lines are driven by the group of the first gate drive circuits, and amplitude values of signals detected by the receive circuits connected with the groups of second touch detection lines when the group of second gate lines are driven by the group of second gate drive circuits. 10. The display driver according to claim 9 , further comprising a plurality of source drive circuits operable to drive the plurality of source lines respectively, wherein the plurality of source drive circuits are capable of exercising control so as to m

Assignees

Inventors

Classifications

  • Improving the luminance or brightness uniformity across the screen · CPC title

  • Electrode mesh in capacitive digitiser: electrode for touch sensing is formed of a mesh of very fine, normally metallic, interconnected lines that are almost invisible to see. This provides a quite large but transparent electrode surface, without need for ITO or similar transparent conductive material · CPC title

  • by capacitive means · CPC title

  • suitable for active matrices only · CPC title

  • Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title

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What does patent US9640130B2 cover?
A display driver is connectable with and serves to activate an active matrix type display panel having a plurality of source lines wired to run in an up-and-down direction and a plurality of gate lines wired to run in left and right directions when viewed from a direction perpendicular to a substrate, and a plurality of pixels respectively arranged at intersections where the source and gate lin…
Who is the assignee on this patent?
Synaptics Japan Gk
What technology area does this patent fall under?
Primary CPC classification G09G3/3696. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 02 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).