Array substrate, method for manufacturing the same, and display device

US9252163B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9252163-B1
Application numberUS-201514739056-A
CountryUS
Kind codeB1
Filing dateJun 15, 2015
Priority dateSep 2, 2014
Publication dateFeb 2, 2016
Grant dateFeb 2, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

In the present disclosure, it is provided an array substrate including a pad area, signal lines arranged on the substrate, conductive connection lines arranged at least on the pad area and directly connected to a flexible circuit, and conductive connection lines arranged at least on the pad area and directly connected to a flexible circuit. The conductive connection lines may be connected to the signal lines through a via hole, and may include a first wire and a second wire electrically connected to each other. The second wire may be arranged in such a manner that a contact area between the conductive connection lines and the flexible circuit is not less than a predetermined threshold when the flexible circuit is displaced in a first direction relative to the first wire. The first direction may be substantially perpendicular to an extending direction of the first wire.

First claim

Opening claim text (preview).

What is claimed is: 1. An array substrate, comprising: a pad area; signal lines, arranged on the pad area; and conductive connection lines, arranged at least on the pad area and directly connected to a flexible circuit, wherein the conductive connection lines are connected to the signal lines through a via hole, and comprise a first wire and a second wire electrically connected to each other; wherein the second wire is arranged in such a manner that a contact area between the conductive connection lines and the flexible circuit is not less than a predetermined threshold when the flexible circuit is displaced in a first direction relative to the first wire; and wherein the first direction is substantially perpendicular to an extending direction of the first wire. 2. The array substrate according to claim 1 , wherein in the pad area, a pattern of the signal lines in a direction substantially perpendicular to the array substrate coincides with a pattern of the conductive connection lines. 3. The array substrate according to claim 1 , wherein the extending direction of the first wire is substantially parallel to the flexible circuit. 4. The array substrate according to claim 1 , wherein an extending direction of the second wire is substantially perpendicular to the extending direction of the first wire. 5. The array substrate according to claim 1 , wherein the conductive connection lines are made of Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). 6. The array substrate according to claim 1 , wherein the signal lines are gate lines, data lines or common electrode lines. 7. The array substrate according to claim 6 , further comprising: an insulation layer, arranged to enable the gate lines, the data lines or the common electrode lines to be insulated from each other. 8. The array substrate according to claim 7 , wherein the insulation layer comprises a gate insulation layer and a passivation layer. 9. The array substrate according to claim 4 , wherein the conductive connection lines are in a shape of “+”, “ ” or “ ”. 10. A display device, comprising: an array substrate; and a flexible circuit connected to the array substrate via conductive connection lines, the array substrate comprises: a pad area; signal lines arranged on the pad area; and the conductive connection lines arranged at least on the pad area and directly connected to the flexible circuit, wherein the conductive connection lines are connected to signal lines through a via hole, and comprise a first wire and a second wire electrically connected to each other; wherein the second wire is arranged in such a manner that a contact area between the conductive connection lines and the flexible circuit is not less than a predetermined threshold when the flexible circuit is displaced in a first direction relative to the first wire; and wherein the first direction is substantially perpendicular to an extending direction of the first wire. 11. The display device according to claim 10 , wherein in the pad area, a pattern of the signal lines in a direction substantially perpendicular to the array substrate coincides with a pattern of the conductive connection lines. 12. The display device according to claim 10 , wherein the extending direction of the first wire is substantially parallel to the flexible circuit. 13. The display device according to claim 10 , wherein an extending direction of the second wire is substantially perpendicular to the extending direction of the first wire. 14. The display device according to claim 10 , wherein the conductive connection lines are made of Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). 15. The display device according to claim 10 , wherein the signal lines are gate lines, data lines or common electrode lines. 16. The display device according to claim 15 , further comprising: an insulation layer arranged to enable the gate lines, the data lines or the common electrode lines to be insulated from each other. 17. The display device according to claim 16 , wherein the insulation layer comprises a gate insulation layer and a passivation layer. 18. The display device according to claim 13 , wherein the conductive connection lines are in a shape of “+”, “ ” or “ ”. 19. A method for manufacturing an array substrate comprising a pad area, the method comprising: depositing a metal film, and forming a pattern of signal lines by a patterning process; and depositing a conductive film, and forming a pattern of conductive connection lines at least on the pad area by another patterning process, so that the conductive connection lines are connected to the signal lines through a via hole, and comprise a first wire and a second wire electrically connected to each other; wherein the second wire is arranged in such a manner that a contact area between the conductive connection lines and the flexible circuit is not less than a predetermined threshold when the flexible circuit is displaced in a first direction relative to the first wire; and wherein the first direction is substantially perpendicular to an extending direction of the first wire. 20. The method according to claim 19 , wherein in the pad area, a pattern of the signal lines in a direction substantially perpendicular to the array substrate coincides with a pattern of the conductive connection lines.

Assignees

Inventors

Classifications

  • H10D86/441Primary

    Interconnections, e.g. scanning lines · CPC title

  • H10D86/60Primary

    wherein the TFTs are in active matrices · CPC title

  • Electricity · mapped topic

  • H01L27/124Primary

    Electricity · mapped topic

  • Conductors connecting driver circuitry and terminals of panels · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9252163B1 cover?
In the present disclosure, it is provided an array substrate including a pad area, signal lines arranged on the substrate, conductive connection lines arranged at least on the pad area and directly connected to a flexible circuit, and conductive connection lines arranged at least on the pad area and directly connected to a flexible circuit. The conductive connection lines may be connected to th…
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Hefei Xinsheng Optoelectronics Technology Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D86/441. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 02 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).