Gate driving circuit having forward and reverse scan directions and display apparatus implementing the gate driving circuit

Patent metadata

Field	Value
Publication number	US-9406272-B2
Application number	US-201113301637-A
Country	US
Kind code	B2
Filing date	Nov 21, 2011
Priority date	May 18, 2011
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

A gate driving circuit includes a shift register and a vertical start line. The shift register includes first to N-th circuit stages sequentially providing first to N-th gate-on signals to first to N-th gate lines, respectively, at least one reverse dummy stage adjacent to the first circuit stage and at least one forward dummy stage adjacent to the N-th circuit stage (N is a natural number). The vertical start line is electrically connected to the first circuit stage or the N-th circuit stage according to a scan direction and transfers a vertical start signal to the first or N-th circuit stage.

First claim

What is claimed is:

1. A gate driving circuit, comprising:
a shift register including first to N-th circuit stages sequentially providing first to N-th gate-on signals to first to N-th gate lines, respectively, at least one reverse dummy stage adjacent to the first circuit stage, and at least one forward dummy stage adjacent to the N-th circuit stage, wherein N is a natural number; and
a vertical start line electrically connected to the first circuit stage or the N-th circuit stage according to a scan direction of the gate lines, wherein the vertical start line transfers a vertical start signal to the first or N-th circuit stage, wherein the shift register includes an n-th circuit stage, wherein n is a natural number, outputting an n-th gate-on signal, wherein the n-th circuit stage comprises:
a pull-up control part applying a carry signal of one of previous circuit stages to a control node in response to the carry signal of one of the previous circuit stages before the n-th gate-on signal is outputted according to the scan direction;
a pull-up part outputting a clock signal as the n-th gate-on signal in response to a signal applied to the control node;
a carry part outputting the clock signal as an n-th carry signal in response to the signal applied to the control node;
a first pull-down part pulling down the signal applied to the control node to a first off signal in response to a carry signal of a first next circuit stage after the n-th gate-on signal is outputted; and
a second pull-down part pulling down the n-th gate-on signal to the first off signal in response to the carry signal of the first next circuit stage, wherein the n-th circuit stage further comprises:
a reset part pulling down the signal applied to the control node to a second off signal in response to a carry signal of a second next circuit stage, and wherein when the scan direction is the forward direction, the shift register further includes a first forward dummy stage including a carry part electrically connected to first and second pull-down parts of the N-th circuit stage and a second forward dummy stage electrically connected to a reset part of the N-th circuit stage, and
when the scan direction is the reverse direction, the shift register further includes a first reverse dummy stage including a carry part electrically connected to first and second pull-down parts of the first circuit stage and a second reverse dummy stage electrically connected to a reset part of the first circuit stage.

2. A gate driving circuit, comprising:
a shift register including first to N-th circuit stages sequentially providing first to N-th gate-on signals to first to N-th gate lines, respectively, at least one reverse dummy stage adjacent to the first circuit stage, and at least one forward dummy stage adjacent to the N-th circuit stage, wherein N is a natural number;
a vertical start line electrically connected to the first circuit stage or the N-th circuit stage according to a scan direction of the gate lines, wherein the vertical start line transfers a vertical start signal to the first or N-th circuit stage;
a falling circuit including first to N-th falling stages which sequentially drop the first to the N-th gate-on signals applied to the first to N-th gate lines to the first off signal; and
an auxiliary off line connected to the first to N-th falling stages, wherein the first off signal is transferred to the auxiliary off line, wherein each of the first to N-th falling stages comprises:
a forward direction transistor dropping a gate-on signal applied to a gate line to the first off signal when the scan direction is the forward direction; and
a reverse direction transistor dropping a gate-on signal applied to a gate line to the first off signal when the scan direction is the reverse direction, wherein the falling circuit includes an n-th falling stage, wherein n is a natural number, and wherein when the scan direction is the forward direction,
the forward direction transistor of the n-th falling stage includes a control electrode electrically connected to an (n+1)-th gate line, an input electrode electrically connected to an n-th gate line, and an output electrode electrically connected to the auxiliary off line, and
the reverse direction transistor of the n-th falling stage includes a control electrode which is electrically floated.

3. A gate driving circuit, comprising:
a shift register including first to N-th circuit stages sequentially providing first to N-th gate-on signals to first to N-th gate lines, respectively, at least one reverse dummy stage adjacent to the first circuit stage, and at least one forward dummy stage adjacent to the N-th circuit stage, wherein N is a natural number;
a vertical start line electrically connected to the first circuit stage or the N-th circuit stage according to a scan direction of the gate lines, wherein the vertical start line transfers a vertical start signal to the first or N-th circuit stage;
a falling circuit including first to N-th falling stages which sequentially drop the first to the N-th gate-on signals applied to the first to N-th gate lines to the first off signal; and
an auxiliary off line connected to the first to N-th falling stages, wherein the first off signal is transferred to the auxiliary off line, wherein each of the first to N-th falling stages comprises:
a forward direction transistor dropping a gate-on signal applied to a gate line to the first off signal when the scan direction is the forward direction; and
a reverse direction transistor dropping a gate-on signal applied to a gate line to the first off signal when the scan direction is the reverse direction, wherein the falling circuit includes an n-th falling stage, wherein n is a natural number, and wherein when the scan direction is the reverse direction,
the reverse direction transistor of the n-th falling stage includes a control electrode electrically connected to an (n−1)-th gate line, an input electrode electrically connected to an n-th gate line, and an output electrode electrically connected to the auxiliary off line, and the forward direction transistor of the n-th falling stage includes a control electrode which is electrically floated.

4. A display apparatus, comprising:
a display panel including a display area and a peripheral area surrounding the display area, the display panel including first to N-th gate lines sequentially arranged in a forward direction in the display area, wherein N is a natural number;
a data driving circuit sequentially providing data signals to the display panel n the forward direction;
a shift register disposed in the peripheral area, the shift register including first to N-th circuit stages respectively generating first to N-th gate-on signals, at least one reverse dummy stage adjacent to the first circuit stage, and at least one forward dummy stage adjacent to the N-th circuit stage;
a vertical start line electrically connected to the first circuit stage and electrically floated with respect to the N-th circuit stage, wherein the vertical start line transfers a vertical start signal to the first circuit stage;
a falling circuit in the peripheral area opposite to an area in which the shift register is disposed, the falling circuit including first to N-th falling stages which sequentially drop the first to N-th gate-on signals applied to the first to N-th gate lines to the first off signal, wherein each of the first to N-th falling stages includes a forward direction transistor and a reverse direction transistor; and
an auxiliary off line adjacent to the falling circuit,
wherein the first off signal is transferred to the auxiliary off line,
wherein the falling circuit includes an n-th falling stage,
wherein the forward direction transistor of the n-th falling stage includes a control electrode elec

Assignees

• Lee Jae-Hoon
• Koo Bon-Yong
• Moon Seung-Hwan
• Lee Won-Hee
• Samsung Display Co Ltd

Inventors

• Lee Jae-Hoon
• Koo Bon-Yong
• Moon Seung-Hwan
• Lee Won-Hee

Classifications

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2310/0283

  Arrangement of drivers for different directions of scanning · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title