Drain-extended transistor

Patent metadata

Field	Value
Publication number	US-11456381-B2
Application number	US-202017123835-A
Country	US
Kind code	B2
Filing date	Dec 16, 2020
Priority date	Dec 16, 2020
Publication date	Sep 27, 2022
Grant date	Sep 27, 2022

Abstract

Described examples include an integrated circuit having a semiconductor substrate. The integrated circuit has a transistor that includes a buried layer having within the substrate, the buried layer defining a drift region between the buried layer and the top surface and a body region in the substrate extending from the buried layer to the surface of the substrate. The transistor also having a source formed in the body region, a drain extending from the buried layer to the surface of the substrate, a drift well extending from the buried layer toward the top surface and extending from the body region to the drain, a drift surface layer located between the drift well and the top, and a gate proximate to the surface of the substrate at the body region.

First claim

What is claimed is:

1. An integrated circuit comprising:
a semiconductor substrate having a first conductivity type and a top surface;
a transistor including:
a buried layer having a second conductivity type within the semiconductor substrate, the buried layer defining a drift region between the buried layer and the top surface;
a body region in the semiconductor substrate extending from the buried layer to the top surface of the semiconductor substrate and having the second conductivity type;
a source having the first conductivity type formed in the body region;
a drain having the first conductivity type and extending from the buried layer to the top surface of the semiconductor substrate;
a drift well having the second conductivity type, the drift well extending from the buried layer toward the top surface and extending from the body region to the drain;
a drift surface layer having the first conductivity type and located between the drift well and the top surface; and
a gate proximate to the top surface of the semiconductor substrate at the body region;
wherein the drift surface layer extends under the gate toward the source further than the drift well extends under the gate toward the source.

2. The integrated circuit of claim 1 , wherein the buried layer is a first buried layer, and further comprising an adjacent device having a second buried layer spaced apart from the first buried layer, wherein the drift well extends beyond the drift surface layer toward the second buried layer.

3. The integrated circuit of claim 1 , wherein the transistor is a high-side switch of a high-voltage drive circuit.

4. The integrated circuit of claim 1 , wherein the buried layer has a graded dopant concentration that increases toward the source and decreases toward the drain.

5. The integrated circuit of claim 2 , wherein the drift well extends beyond the drift surface layer toward the second buried layer by at least 1 μm.

6. The integrated circuit of claim 1 , wherein the semiconductor substrate is crystalline silicon.

7. The integrated circuit of claim 1 , wherein the first conductivity type is p-type, and the second conductivity type is n-type.

8. A transistor comprising:
a buried layer having a second conductivity type in a semiconductor substrate having a first conductivity type, the buried layer spaced apart from a top surface of the semiconductor substrate and defining a drift region between the buried layer and the top surface;
a body region having the second conductivity type located in the semiconductor substrate and extending from the top surface toward the buried layer;
a source having the first conductivity type formed in the body region;
a drift well extending from the buried layer to the top surface of the semiconductor substrate and touching the body region;
a drain having the first conductivity type and extending from the top surface of the semiconductor substrate into the drift well;
a drift surface layer having the first conductivity type between the top surface and the drift well; and
a gate over the body region and between the source and the drift well;
wherein the drift surface layer extends under the gate toward the source further than the drift well extends under the gate toward the source.

9. The transistor of claim 8 wherein the drift well extends beyond the drift surface layer along a periphery of the drift well.

10. The transistor of claim 8 , wherein the buried layer is a first buried layer spaced apart from a second buried layer of an adjacent device by a transition region, and the drift well extends toward the second buried layer in the transition region further than the drift surface layer extends toward the second buried layer in the transition region.

11. The transistor of claim 8 , wherein the drift surface layer has a first dopant concentration at least four orders of magnitude greater than a second dopant concentration of the drift well.

12. The transistor of claim 8 , wherein the first conductivity type is p-type, and the conductivity type is n-type.

13. The transistor of claim 8 , wherein the buried layer has a graded dopant concentration that increases toward the source and decreases toward the drain.

14. A method comprising:
forming a buried region in a substrate, the substrate having a first conductivity type and the buried region having a second conductivity type, the buried region defining a drift region between the buried region and a surface of the substrate;
forming a body region having the second conductivity type extending from the surface of the substrate toward the buried region;
forming a drain having the first conductivity type and extending from the surface of the substrate toward the buried region, wherein at least a portion of the drift region is between the body region and the drain;
forming a drift well having the second conductivity type in the drift region;
forming a drift surface layer having the first conductivity type between the drift well and the surface of the substrate;
forming a source having the first conductivity type in the body region; and
forming a gate proximate to the body region between the source and the drift region;
wherein the drift surface layer extends under the gate toward the source further than the drift well extends under the gate toward the source.

15. The method of claim 14 , further comprising forming a gate oxide between the gate and the body region.

16. The method of claim 14 , wherein the first conductivity type is p-type, and the second conductivity type is n-type.

17. The method of claim 14 , wherein the buried region is a first buried region and further comprising forming diode including a second buried region spaced apart from the first buried region, wherein the drift well extends past the drift surface layer toward the second buried region.

18. The method of claim 14 , wherein the substrate includes an underlying substrate and an epitaxial layer.

19. The method of claim 14 , further comprising forming a field oxide on the surface of the substrate between the body region and the drain.

20. A transistor comprising:
a buried layer having a second conductivity type in a semiconductor substrate having a first conductivity type, the buried layer spaced apart from a top surface of the semiconductor substrate and defining a drift region between the buried layer and the top surface;
a body region having the second conductivity type located in the semiconductor substrate and extending from the top surface toward the buried layer;
a source having the first conductivity type formed in the body region;
a drift well extending from the buried layer to the top surface of the semiconductor substrate and touching the body region;
a drain having the first conductivity type and extending from the top surface of the semiconductor substrate into the drift well;
a drift surface layer having the first conductivity type between the top surface and the drift well; and
a gate over the body region and between the source and the drift well;
wherein the drift surface layer has a first dopant concentration at least four orders of magnitude greater than a second dopant concentration of the drift well.

Assignees

• Texas Instruments Inc

Inventors

• Lee Meng-Chia
• Kim Sunglyong
• Sridhar Seetharaman
• Pendharkar Sameer

Classifications

• H01L29/66628

  Electricity · mapped topic

• H01L29/7838 Primary

  Electricity · mapped topic

• H01L29/1045

  Electricity · mapped topic

• H01L29/7817

  Electricity · mapped topic

• H10D62/129

  Cathode regions of diodes · CPC title