LDMOS device with body diffusion self-aligned to gate

Patent metadata

Field	Value
Publication number	US-9887288-B2
Application number	US-201514957223-A
Country	US
Kind code	B2
Filing date	Dec 2, 2015
Priority date	Dec 2, 2015
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

A laterally diffused metal oxide semiconductor (LDMOS) device includes a substrate having a p-epi layer thereon, a p-body region in the p-epi layer and an ndrift (NDRIFT) region within the p-body to provide a drain extension region. A gate stack includes a gate dielectric layer over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region. A patterned gate electrode is on the gate dielectric. A DWELL region is within the p-body region. A source region is within the DWELL region, and a drain region is within the NDRIFT region. An effective channel length (Leff) for the LDMOS device is 75 nm to 150 nm which evidences a DWELL implant that utilized an edge of the gate electrode to delineate an edge of a DWELL ion implant so that the DWELL region is self-aligned to the gate electrode.

First claim

The invention claimed is:

1. A method of forming a laterally diffused metal oxide semiconductor (LDMOS) device, comprising:
providing a substrate having a p-epi layer thereon;
forming a p-body region in said p-epi layer by implanting a blanket p-buried layer (PBL) implant;
forming an NDRIFT region by implanting an NDRIFT ion implant within said p-body region in said p-epi layer;
forming a gate dielectric layer over a surface channel region of said p-epi layer adjacent to and on respective sides of a junction with said NDRIFT region;
forming a patterned gate electrode on said gate dielectric layer;
forming a DWELL region by implanting a first post-gate well ion implant comprising a p-type dopant into said p-body region in said p-epi layer, wherein at least one edge of said gate electrode is included in a photomask opening for said first post-gate well ion implant so that said gate electrode delineates an edge of said first post-gate well ion implant; and
forming a source region within said DWELL region and a drain region within said NDRIFT region.

2. The method of claim 1 , wherein forming the p-body region further comprises annealing said PBL implant.

3. The method of claim 1 , further comprising forming sidewall spacers on sidewalls of said gate electrode before forming said source region and said drain region.

4. The method of claim 1 , wherein said p-type DWELL ion implant comprises boron with an energy between 15 and 30 KeV, an angle less than 5 degrees, and a dose between 8×10 13 cm −2 and 3.0×10 14 cm −2 .

5. The method of claim 1 , further comprising forming an n-type DWELL region within said DWELL region by implanting a second post-gate well ion implant comprising an n-type dopant.

6. The method of claim 5 , wherein said second post-gate well ion implant comprises arsenic with an energy from 10 to 30 KeV and a dose from 4×10 14 cm −2 to 1.2×10 15 cm −2 .

7. The method of claim 1 , further comprising forming an isolation tank comprising forming an n+ buried layer (NBL) in said p-epi layer before forming said NDRIFT region, and an n+ sinker providing vertical walls coupling a top surface of said p-epi layer to said NBL.

8. The method of claim 1 , further comprising forming a local oxidation (LOCOS) layer over a portion of said NDRIFT region, wherein said gate electrode is formed on at least a portion of said LOCOS layer.

9. The method of claim 1 , wherein an effective channel length (Leff) for said LDMOS device is 75 nm to 150 nm.

10. The method of claim 1 , wherein said LDMOS device comprises a channel region that extends between said DWELL region and said NDRIFT region.

11. The method of claim 1 , further comprising forming a shallow n-well region within said NDRIFT region and forming a shallow p-well region outside of said NDRIFT region.

12. The method of claim 11 , wherein said DWELL region is formed over said shallow p-well region.

13. The method of claim 11 , wherein said drain region is formed within said shallow n-well region in said NDRIFT region.

14. A method of forming a laterally diffused metal oxide semiconductor (LDMOS) device, comprising:
providing a substrate;
forming a p-epi layer on the substrate;
forming a p-body region within the p-epi layer;
forming an NDRIFT region within the p-body region;
forming a gate dielectric layer over a surface channel region adjacent to and on respective sides of a junction between the NDRIFT region and the p-body region;
forming a gate electrode on the gate dielectric layer;
forming a DWELL region in the p-body region, wherein at least one edge of the gate electrode delineates an edge in the forming of the DWELL region;
forming a source region within the DWELL region; and
forming a drain region within the NDRIFT region.

15. The method of claim 14 , comprising forming sidewall spacers on sidewalls of the gate electrode before forming the source region and the drain region.

16. The method of claim 14 , wherein forming the p-body region comprises implanting a blanket p-buried layer (PBL) implant.

17. The method of claim 14 , comprising forming an n-type DWELL region within the DWELL region.

18. The method of claim 14 , comprising forming a shallow n-well region within the NDRIFT region and forming a shallow p-well region outside of the NDRIFT region.

19. The method of claim 18 , wherein the DWELL region is formed over the shallow p-well region.

20. The method of claim 18 , wherein the drain region is formed within the shallow n-well region.

Assignees

• Texas Instruments Inc

Inventors

• Edwards Henry Litzmann
• Hu Binghua
• Todd James Robert

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H01L29/0696

  Electricity · mapped topic