High-voltage drain extended mos transistor

Patent metadata

Field	Value
Publication number	US-2019206997-A1
Application number	US-201815876989-A
Country	US
Kind code	A1
Filing date	Jan 22, 2018
Priority date	Dec 29, 2017
Publication date	Jul 4, 2019
Grant date	—

Abstract

A semiconductor device includes a MOS transistor located within a semiconductor substrate of a first conductivity type. The transistor includes a body well located between a drain well and a substrate contact well. A buried voltage blocking region of a second conductivity type is located within the substrate and is connected to the body well. The buried voltage blocking region extends toward the substrate contact well, with an unmodified portion of the substrate remaining between the voltage blocking region and the substrate contact well.

First claim

1 - 7 . (canceled)

8 . A method of forming an electronic device, comprising:
forming within a semiconductor substrate a body well and a drain well of a drain-extended (DE)-MOS transistor; and forming within said semiconductor substrate a junction termination diode having first and second terminals, said first terminal connected to the substrate at a substrate contact well, and said second terminal connected to said body well.

9 . The method of claim 8 , wherein said semiconductor substrate includes an epitaxial layer of a first conductivity type, and said substrate contact well has said first conductivity type, and further comprising forming in said epitaxial layer a buried region of a second conductivity type extending from said body well toward said substrate contact well, wherein an epitaxial layer portion is located between said buried region and said substrate contact well, said epitaxial layer portion having a lower dopant concentration than said substrate contact well.

10 . The method of claim 9 , wherein said buried region extends between about 20 μm and about 200 μm from said body well toward said anode region.

11 . The method of claim 9 , wherein said second terminal is coincident with said body well.

12 . The method of claim 8 , wherein said junction termination diode has a breakdown voltage of at least about 700 V.

13 . The method of claim 9 , further comprising forming an HV well of said second conductivity type located between said body well and said drain well of said MOS transistor, said HV well partially overlapping said buried region.

14 . The method of claim 9 , wherein said buried region extends from said body well toward said drain well with a graded dopant profile.

15 - 20 . (canceled)

21 . A method of forming an integrated circuit, comprising:
forming first and second doped regions of a first conductivity type within a semiconductor substrate of the first conductivity type; forming a third doped region of a second conductivity type located within the substrate between the first and second doped regions; forming a fourth doped region of the first conductivity type at a surface of the substrate and located between and connected to the first doped region and the third doped region; forming a gate electrode over the third doped region; and forming a buried layer having the second conductivity type within the substrate, the third doped region located between the buried layer and the gate electrode, the buried layer partially extending from the third doped region toward the first doped region, wherein the second doped region and the buried layer are spaced apart laterally.

22 . The method as recited in claim 21 , wherein the first conductivity type is p-type and the second conductivity type is n-type.

23 . The method as recited in claim 21 , further comprising forming a fifth doped region having the second conductivity type located between and the first doped region and the third doped region, and between the buried layer and the fourth doped region.

24 . The method as recited in claim 21 , wherein the buried layer extends from the third doped region toward the first doped region with a graded dopant profile.

25 . The method as recited in claim 21 , wherein the second and third doped regions are configured to receive a potential capable of fully depleting a region of the substrate between the buried layer and a surface of the substrate.

26 . The method as recited in claim 21 , wherein the buried layer extends at least about 20 μm from the third doped region toward the second doped region.

27 . The method as recited in claim 21 , wherein the buried layer has a graded dopant profile that decreases in a direction from the third doped region toward the first doped region

28 . A method of forming an integrated circuit, comprising:
forming a source region and a drain region having a first conductivity type in a semiconductor substrate having the first conductivity type; forming a buried layer having a second conductivity type that extends under the source region and the drain region; forming a first well region having the second conductivity type that extends from the source region to the buried layer; and forming a second well region of the first conductivity type in the semiconductor substrate spaced apart from the first well region, wherein a semiconductor substrate portion is located between the second well region and the buried layer, the substrate portion having a lower dopant concentration than the second well region.

29 . The method as recited in claim 28 , further comprising forming a surface well region having the first conductivity type that extends from the first well region to a third well region having the first conductivity type.

30 . The method as recited in claim 29 , wherein the buried layer has a graded dopant profile such that a concentration of a dopant of the second conductivity type decreases from the first well region toward the third well region.

31 . The method as recited in claim 29 , further comprising forming a buried well region having the second conductivity type between the surface well region and the buried layer, the buried well region extending from the first well to the third well.

32 . The method as recited in claim 28 , wherein the substrate portion extends between the first well and the second well at the substrate surface.

33 . The method as recited in claim 28 , wherein the first conductivity type is p-type and the second conductivity type is n-type.

Assignees

• Texas Instruments Inc

Inventors

• Kim Sunglyong
• Sridhar Seetharaman
• Pendharkar Sameer

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P30/22

  using masks · CPC title

• H01L29/0623

  Electricity · mapped topic

• H01L29/7816

  Electricity · mapped topic