Integrated assemblies having voids along regions of gates, and methods of forming conductive structures

Patent metadata

Field	Value
Publication number	US-11456299-B2
Application number	US-202117318940-A
Country	US
Kind code	B2
Filing date	May 12, 2021
Priority date	Dec 26, 2019
Publication date	Sep 27, 2022
Grant date	Sep 27, 2022

Abstract

Some embodiments include an integrated assembly with a semiconductor-material-structure having a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. The semiconductor-material-structure has a first side and an opposing second side. A first conductive structure is adjacent to the first side and is operatively proximate the channel region to gatedly control coupling of the first and second source/drain regions through the channel region. A second conductive structure is adjacent to the second side and is spaced from the second side by an intervening region which includes a void. Some embodiments include methods of forming integrated assemblies.

First claim

I claim:

1. A method of forming an integrated assembly, comprising:
forming linear features over a base; the linear features including digit lines and semiconductor-material-linear-configurations over the digit lines; the linear features extending along a first direction;
forming trenches to extend into the linear features; the trenches extending along a second direction which crosses the first direction; the trenches extending into the semiconductor-material-linear-configurations but not breaking the digit lines; the trenches patterning semiconductor-material-structures from the semiconductor-material-linear-configurations; the semiconductor-material-structures including semiconductor-material-pillars; the semiconductor-material-structures including upper source/drain regions at upper regions of the semiconductor-material-pillars, channel regions within the semiconductor-material-pillars and under the upper source/drain regions, and lower source/drain regions under the channel regions and coupled with the digit lines;
forming first-material-liners within the trenches;
forming second-material-liners over the first-material-liners;
recessing the second-material-liners along first sides of the trenches while not recessing the second-material-liners along opposing second sides of the trenches;
forming gate lines within the trenches and over the recessed second-material-liners;
after forming the gate lines, recessing the second-material-liners along the second sides of the trenches to form voids; and
capping the voids.

2. The method of claim 1 wherein the first-material-liners comprise carbon-doped silicon dioxide.

3. The method of claim 2 wherein the second-material-liners comprise silicon nitride.

4. The method of claim 1 further comprising forming storage elements coupled with the upper source/drain regions.

5. The method of claim 4 wherein the storage elements are capacitors.

6. The method of claim 1 wherein the recessing of the second-material-liners along the first sides of the trenches exposes regions of the first-material-liners; and further comprising removing the exposed regions of the first-material-liners and replacing them with insulative material.

7. The method of claim 1 wherein the recessing of the second-material-liners along the first sides of the trenches exposes regions of the first-material-liners; wherein the first-material-liners comprise carbon-doped silicon dioxide; and further comprising oxidizing the exposed regions of the first-material-liners to convert them to silicon dioxide.

8. The method of claim 1 wherein at least portions of the lower source/drain regions are within portions of the semiconductor-material-structures which are under the pillars and not patterned into the pillars.

9. The method of claim 1 further comprising forming insulative material between the linear features, and forming the trenches to extend into the insulative material as well as into the linear features.

10. The method of claim 9 wherein the linear features are spaced from one another by gaps, and further comprising forming linear-feature-liners along the linear features and within the gaps; and wherein the forming of the insulative material between the linear features comprises forming the insulative material over the linear-feature-liners and within the gaps.

11. The method of claim 10 wherein the linear-feature-liners comprise a same material as the first-material-liners.

12. The method of claim 11 wherein said same material is carbon-doped silicon dioxide.

13. The method of claim 1 wherein the capping of the voids comprises capping the voids with silicon dioxide.

14. A method of forming integrated assembly, comprising:
forming a semiconductor-material-structure having a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions; the semiconductor-material-structure having a first side and an opposing second side;
forming a first conductive structure adjacent the first side and operatively proximate the channel region to gatedly control coupling of the first and second source/drain regions through the channel region; and
forming a second conductive structure adjacent the second side and spaced from the second side by an intervening region which includes a void.

15. The method of claim 14 wherein the intervening region includes carbon-doped silicon dioxide between the semiconductor-material-structure and the void.

16. The integrated method of claim 15 wherein the carbon concentration within the carbon-doped silicon dioxide is at least about 1 at %.

17. The method of claim 15 wherein the carbon concentration within the carbon-doped silicon dioxide is at least about 5 at %.

18. The method of claim 15 wherein the carbon concentration within the carbon-doped silicon dioxide is at least about 10 at %.

19. The method of claim 14 wherein first conductive structure is spaced from the first side by only an insulative material comprising silicon dioxide.

20. The method of claim 14 wherein the first and second conductive structures each include a metal-containing-region directly against a doped-semiconductor-containing-region.

Assignees

• Micron Technology Inc

Inventors

• Tang Sanh D

Classifications

• H01L27/10873

  Electricity · mapped topic

• H01L27/10885

  Electricity · mapped topic

• H01L27/10852

  Electricity · mapped topic

• H01L27/10814 Primary

  Electricity · mapped topic

• H01L27/10891

  Electricity · mapped topic