Information processing apparatus
US-2024385843-A1 · Nov 21, 2024 · US
Dual issuing of complex instruction set instructions
US9104399B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9104399-B2 |
| Application number | US-64571609-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 23, 2009 |
| Priority date | Dec 23, 2009 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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- Title
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Abstract
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A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for issuing a processor instruction to multiple processing sections, the method comprising: accepting, at an instruction issue unit within a processor, an instruction that is to be issued as a first micro-op to a first execution unit of the processor and a second micro-op to a second execution unit of the processor, the first micro-op causing the first execution unit to determine intermediate data to be provided to the second execution unit for use…
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- G06F9/3001Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9104399B2 cover?
- A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked in…
- Who is the assignee on this patent?
- Busaba Fadi, Curran Brian, Eisen Lee, and 4 more
- What technology area does this patent fall under?
- Primary CPC classification G06F9/3001. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).