Lithium drifted thin film transistors for neuromorphic computing

Patent metadata

Field	Value
Publication number	US-11444207-B2
Application number	US-201816217651-A
Country	US
Kind code	B2
Filing date	Dec 12, 2018
Priority date	Dec 12, 2018
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

A semiconductor device includes a field-effect transistor, a first back-end-of-line (BEOL) metallization level and a second BEOL metallization level disposed above the first BEOL metallization level. A portion of the field-effect transistor includes lithium therein, and the field-effect transistor is integrated between the first and second BEOL metallization levels. The portion of the field-effect transistor including the lithium therein can be a channel layer, or a source and/or drain region.

First claim

We claim:

1. A semiconductor device, comprising:
a field-effect transistor, wherein a portion of the field-effect transistor comprises lithium therein;
a first back-end-of-line metallization level; and
a second back-end-of-line metallization level disposed above the first back-end-of-line metallization level;
wherein the field-effect transistor is integrated between the first and second back-end-of-line metallization levels;
wherein the field-effect transistor comprises a channel layer, a source region, a drain region, a gate dielectric layer disposed on top surfaces of the channel layer, the source region and the drain region, and a gate disposed on a top surface of the gate dielectric layer;
wherein the source region and the drain region comprise the lithium therein;
wherein the lithium in the source region is at a higher concentration at an upper portion than at a lower portion of the source region;
wherein the lithium in the drain region is at a higher concentration at an upper portion than at a lower portion of the drain region; and
wherein the source region and the drain region are electrically connected to one or more contacts in the second back-end-of-line metallization level by respective vias located between the first and second back-end-of-line metallization levels and extending through the gate dielectric layer.

2. The semiconductor device according to claim 1 , wherein the channel layer further comprises one of amorphous silicon, polycrystalline silicon and poly-germanium.

3. The semiconductor device according to claim 1 , further comprising:
a back gate;
wherein the field-effect transistor is disposed on the back gate.

4. The semiconductor device according to claim 3 , further comprising:
a dielectric layer disposed between the field-effect transistor and the back gate.

5. The semiconductor device according to claim 3 , wherein the back gate is disposed on a contact in the first back-end-of-line metallization level.

6. The semiconductor device according to claim 3 , wherein the back gate is electrically connected to a contact in the first back-end-of-line metallization level through a via.

7. A semiconductor device, comprising:
an array of resistive processing unit devices, wherein each resistive processing unit device in the array comprises:
a field-effect transistor integrated between a first back-end-of-line metallization level and a second back-end-of-line metallization level above the first back-end-of-line metallization level;
wherein a portion of each field-effect transistor comprises lithium therein;
wherein each field-effect transistor comprises a channel layer, a source region, a drain region, and a gate dielectric layer disposed on top surfaces of the channel layer, the source region and the drain region;
wherein a gate of each field-effect transistor is electrically connected to a contact of the second back-end-of-line metallization level and is disposed on a top surface of the gate dielectric layer;
wherein the source region and the drain region comprise the lithium therein; and
wherein the lithium in the source region is at a higher concentration at an upper portion than at a lower portion of the source region;
wherein the lithium in the drain region is at a higher concentration at an upper portion than at a lower portion of the drain region; and
wherein the source region and the drain region are electrically connected to one or more contacts in the second back-end-of-line metallization level by respective vias located between the first and second back-end-of-line metallization levels and extending through the gate dielectric layer.

8. The semiconductor device according to claim 7 , wherein the channel layer further comprises one of amorphous silicon, polycrystalline silicon and poly-germanium.

9. The semiconductor device according to claim 1 , wherein a depth of the lithium in each of the source and drain regions is less than a depth of the source and drain regions.

10. The semiconductor device according to claim 9 , wherein the depth of the source and drain regions is about 10 nm to about 100 nm.

11. The semiconductor device according to claim 1 , wherein each of the source and drain regions further comprises a dopant different from the lithium.

12. The semiconductor device according to claim 7 , wherein a depth of the lithium in each of the source and drain regions is less than a depth of the source and drain regions.

13. The semiconductor device according to claim 12 , wherein the depth of the source and drain regions is about 10 nm to about 100 nm.

14. The semiconductor device according to claim 7 , wherein each of the source and drain regions further comprises a dopant different from the lithium.

Assignees

• IBM

Inventors

• Khan Babar
• Li Ning
• Kumar Arvind
• Lee Yun Seog
• De Souza Joel P
• Sadana Devendra K

Classifications

• G06N3/065

  Analogue means · CPC title

• H10D64/01356

  the insulator being formed after the semiconductor body, the semiconductor being a Group IV material and not being silicon, e.g. Ge, SiGe or SiGeC (H10D64/01364, H10D64/01366 take precedence) · CPC title

• H10D64/01348

  with substrate doping, e.g. N, Ge or C implantation, before formation of the insulator · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title