Embedded semiconductor region for latch-up susceptibility improvement

Patent metadata

Field	Value
Publication number	US-2019096886-A1
Application number	US-201815881215-A
Country	US
Kind code	A1
Filing date	Jan 26, 2018
Priority date	Sep 28, 2017
Publication date	Mar 28, 2019
Grant date	—

Abstract

The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.

First claim

What is claimed is:

1 . A metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising:
a first-type substrate; a deep-second-type well in the first-type substrate; a first-type well over the deep-second-type well; a second-type well over the deep-second-type well, wherein the second-type well and the deep-second-type well form an enclosed space that includes the first-type well; and an embedded semiconductor region (ESR) in a vicinity of the enclosed space, the ESR comprising a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.

2 . The MOSFET device of claim 1 , wherein the first-type and the second-type have opposite dopant types, and wherein the ESR is one of an N-type and a P-type structure.

3 . The MOSFET device of claim 2 , wherein a dopant level of the ESR is in a range from about intrinsic doping level to about 10 19 atoms/cm 3 .

4 . The MOSFET device of claim 3 , wherein the dopant level of the ESR is in a range from about 10 15 atoms/cm 3 to about 10 17 atoms/cm 3 .

5 . The MOSFET device of claim 1 , wherein the ESR includes a U-shaped portion in the enclosed space and between the first-type well and an inner sidewall of the enclosed space.

6 . The MOSFET device of claim 5 , wherein the U-shaped portion has a height between about 0.1 μm and about 10 μm between the deep-second-type well and the first-type well and has a width between about 0.1 μm and about 10 μm between the first-type well and the inner sidewall of the enclosed space.

7 . The MOSFET device of claim 6 , wherein the width is between about 0.1 μm and about 5 μm.

8 . The MOSFET device of claim 5 , wherein the ESR further includes a second portion outside and surrounding the enclosed space.

9 . The MOSFET device of claim 8 , wherein the second portion of the ESR has a width between about 0.1 μm and about 10 μm.

10 . The MOSFET device of claim 5 , wherein the ESR further includes a second portion along an outer periphery of the enclosed space.

11 . The MOSFET device of claim 10 , wherein the second portion of the ESR has a width between about 0.5 and about 5 μm.

12 . A method for forming a metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising:
providing a first-type substrate; doping a first portion of the first-type substrate to form a deep-second-type-well in the first-type substrate; doping a second portion of the first-type substrate to form a first-type well; doping a third portion of the first-type substrate to form a second-type well over the deep-second-type well, wherein the deep-second-type well and the second-type well form an enclosed space that includes the first-type well; and doping a fourth portion of the first-type substrate to form an embedded semiconductor region (ESR) in a vicinity of the enclosed space, the ESR comprising a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.

13 . The method of claim 12 , wherein doping the fourth portion of the first-type substrate to form the ESR comprising doping at least a portion of the first-type well with one of an N-type dopant and a P-type dopant.

14 . The method of claim 13 , wherein a dopant concentration of the ESR is in a range from about intrinsic doping level to about 10 19 atoms/cm 3 .

15 . The method of claim 14 , wherein the dopant level of the ESR is in a range from about 10 15 atoms/cm 3 to about 10 17 atoms/cm 3 .

16 . A metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising:
a first-type substrate; a deep-second-type well in the first-type substrate; a first-type well over the second-type well; an second-type well over the deep-second-type well, wherein the second-type well and the deep-second-type well form an enclosed space that includes the first-type well; an isolation structure between the first-type well and the second-type well; at least one MOSFET over the first-type well; and an embedded semiconductor region (ESR) surrounding the first-type well in the enclosed space and under the first-type well and the isolation structure, wherein the ESR comprises a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.

17 . The MOSFET device of claim 16 , wherein the first-type and the second-type have opposite dopant types, and wherein the ESR is one of an N-type and a P-type structure.

18 . The MOSFET device of claim 17 , wherein a dopant level of the ESR is in a range from about intrinsic doping level to about 10 19 atoms/cm 3 .

19 . The MOSFET device of claim 18 , wherein the dopant level of the ESR is in a range of about 10 15 atoms/cm 3 to about 10 17 atoms/cm 3 .

20 . The MOSFET device of claim 16 , wherein the ESR includes a U-shaped portion in the enclosed space and between the first-type well and an inner sidewall of the enclosed space.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Chien Yao
• Su Yu-Ti

Classifications

• H10W15/01

  Manufacture or treatment · CPC title

• H10W15/00

  Highly-doped buried regions of integrated devices · CPC title

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H01L21/823892

  Electricity · mapped topic