Circuit methodology for highly linear and symmetric resistive processing unit

Patent metadata

Field	Value
Publication number	US-9852790-B1
Application number	US-201615335171-A
Country	US
Kind code	B1
Filing date	Oct 26, 2016
Priority date	Oct 26, 2016
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A resistive processing unit (RPU) includes a circuit including at least two current mirrors connected in series, and a capacitor connected with the at least two current mirrors, the capacitor providing a weight based on a charge level of the capacitor. The capacitor is charged or discharged by one of the at least two current mirrors.

First claim

What is claimed is:

1. A resistive processing unit (RPU), comprising:
a circuit including:
at least two current mirrors connected in series; and
a capacitor connected with the at least two current mirrors, the capacitor providing a weight based on a charge level of the capacitor,
wherein the capacitor is charged or discharged by one of the at least two current mirrors.

2. The resistive processing unit according to claim 1 , further comprising a read out transistor connected to the capacitor,
wherein a stored voltage of the capacitor is read out to a gate of an output transistor by the read out transistor.

3. The resistive processing unit according to claim 2 , wherein the output transistor translates the capacitor's voltage to a resistance.

4. The resistive processing unit according to claim 2 , wherein the read out transistor converts the voltage at the capacitor to resistance which is accessible from a source-drain terminals of the read out transistor by applying a read voltage.

5. The resistive processing unit according to claim 1 , wherein the bias voltages to a gate terminal of the current mirror transistors are supplied from and external circuit and also used as a global signal of programming mode for an array of the resistive processing units.

6. The resistive processing unit according to claim 2 , wherein the read out transistor and current mirrors each comprise a complementary-metal-oxide-semiconductor (CMOS) transistor, and
wherein the capacitor is directly connected with the at least two current mirrors.

7. An array of resistive processing units comprising a plurality of the resistive processing units according to claim 1 .

8. The array of resistive processing units according to claim 7 , wherein the plurality of the resistive processing units are configured in a cross-point array to train a neural network.

9. A method of a resistive processing unit (RPU), the method comprising:
charging or discharging a capacitor of the resistive processing unit by one of at least two series connected current mirrors; and
providing a weight based on a charge level of the capacitor connected to the current mirrors.

10. The method according to claim 9 , further comprising reading out a stored voltage of the capacitor to a gate of an output transistor by a read out transistor connected to the capacitor.

11. The method according to claim 10 , further comprising of translating, by the output transistor, a voltage of the capacitor to a resistance value.

12. The method according to claim 9 , further comprising of converting, by a read out transistor connected to the capacitor, the voltage at the capacitor to resistance accessible from source-drain terminals of the read out transistor by applying a read voltage.

13. The method according to claim 9 , further comprising of supplying bias voltages to a gate terminal of the current mirror transistors from and external circuit and also using the bias voltages as a global signal of programming mode for a plurality of the resistive processing units configured in an array.

14. The method according to claim 9 , wherein the read out transistor and current mirrors each comprise a complementary-metal-oxide-semiconductor (CMOS) transistor.

15. The method according to claim 9 , wherein a plurality of the resistive processing units are configured as a cross-point array to train a neural network.

16. An array of resistive processing units (RPUs), each RPU comprising:
a circuit including:
at least two current mirrors that are connected; and
a capacitor connected with the at least two current mirrors, the capacitor providing a weight based on a charge level of the capacitor,
wherein the capacitor is charged or discharged by one of the at least two current mirrors.

17. The array of resistive processing units according to claim 16 , further comprising a read out transistor connected to the capacitor,
wherein a stored voltage of the capacitor is read out to a gate of an output transistor by the read out transistor.

18. The array of resistive processing units according to claim 17 , wherein the output transistor translates the capacitor's voltage to a resistance.

19. The array of resistive processing units according to claim 18 , wherein the read out transistor converts the voltage at the capacitor to resistance which is accessible from source-drain terminal by applying a read voltage, and
wherein the read out transistor and current mirrors each comprise a complementary-metal-oxide-semiconductor (CMOS) transistor.

20. The array of resistive processing units according to claim 16 , wherein bias voltages to a gate terminal of the current mirror transistors are supplied from and external circuit and also used as a global signal of programming mode for each of the resistive processing units.

Assignees

• IBM

Inventors

• Gokmen Tayfun
• Kim Seyoung
• Lee Hyung-Min
• Lee Wooram
• Solomon Paul Michael

Classifications

• G06N3/065

  Analogue means · CPC title

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C13/0038

  Power supply circuits · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title