Three-dimensional semiconductor memory device

Patent metadata

Field	Value
Publication number	US-11444094-B2
Application number	US-202016782737-A
Country	US
Kind code	B2
Filing date	Feb 5, 2020
Priority date	Mar 22, 2019
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

A semiconductor memory device includes a stack structure including electrodes and insulating layers alternately stacked on a substrate, and a vertical channel structure penetrating the stack structure. The vertical channel structure includes a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the electrodes. The vertical insulating layer includes a charge storage layer, a filling insulating layer, and a tunnel insulating layer. The vertical insulating layer has a cell region between the semiconductor pattern and each electrode and a cell separation region between the semiconductor pattern and each insulating layer. A portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer. The filling insulating layer is between the semiconductor pattern and a remaining portion of the charge storage layer of the cell region.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a stack structure comprising a plurality of electrodes and a plurality of insulating layers that are alternately stacked on a substrate; and
a vertical channel structure penetrating the stack structure,
wherein the vertical channel structure comprises a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the plurality of electrodes, and
wherein the vertical insulating layer comprises a charge storage layer, a filling insulating layer, and a tunnel insulating layer,
wherein the vertical insulating layer has a cell region between the semiconductor pattern and each of the plurality of electrodes, and a cell separation region between the semiconductor pattern and each of the plurality of insulating layers,
wherein the charge storage layer comprises a first portion and a remaining portion in the cell region, the first portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer,
wherein the filling insulating layer is between the semiconductor pattern and the remaining portion of the charge storage layer of the cell region, and
wherein the filling insulating layer of the cell region overlaps a corresponding one of the plurality of electrodes in a first direction parallel to the substrate.

2. The semiconductor memory device of claim 1 , wherein
a bottom surface of the cell region and a bottom surface of the electrode adjacent to the cell region are at substantially same levels, respectively, and
a top surface of the cell region and a top surface of the electrode adjacent to the cell region are at substantially same levels, respectively.

3. The semiconductor memory device of claim 1 , wherein the remaining portion of the charge storage layer of the cell region is spaced apart from the tunnel insulating layer across the filling insulating layer.

4. The semiconductor memory device of claim 1 , wherein the tunnel insulating layer is between the charge storage layer and the semiconductor pattern.

5. The semiconductor memory device of claim 1 , wherein the filling insulating layer of the cell separation region is between the charge storage layer and the tunnel insulating layer.

6. The semiconductor memory device of claim 1 , wherein each of the plurality of electrodes includes a protrusion part, which protrudes closer to the semiconductor pattern than an outer sidewall of the charge storage layer of the cell separation region.

7. The semiconductor memory device of claim 6 , wherein the protrusion part has a curved surface.

8. The semiconductor memory device of claim 6 , wherein a maximum thickness of each of the plurality of protrusion parts is less than a maximum thickness of each of the plurality of electrodes, respectively.

9. The semiconductor memory device of claim 1 , wherein
the filling insulating layer of the cell region has a first thickness in a first direction, and
the filling insulating layer of the cell separation region has the second thickness in the first direction, the second thickness being greater than the first thickness.

10. The semiconductor memory device of claim 1 , wherein the charge storage layer has a nonlinear shape between a pair of the plurality of electrodes adjacent to each other in a direction normal to the substrate.

11. A semiconductor memory device, comprising:
a stack structure comprising a plurality of electrodes and a plurality of insulating layers that are alternately stacked on a substrate; and
a vertical channel structure penetrating the stack structure,
wherein the vertical channel structure comprises a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the plurality of electrodes, and
wherein the vertical insulating layer comprises a charge storage layer, a filling insulating layer, and a tunnel insulating layer,
wherein the filling insulating layer and the tunnel insulating layer are between the charge storage layer and the semiconductor pattern,
wherein the vertical insulating layer has a cell region between the semiconductor pattern and each of the plurality of electrodes and a cell separation region between the semiconductor pattern and each of the plurality of insulating layers,
wherein the filling insulating layer of the cell region has a first thickness in a first direction parallel to the substrate,
wherein the filling insulating layer of the cell separation region has a second thickness in the first direction, the second thickness being greater than the first thickness, and
wherein the filling insulating layer of the cell region overlaps a corresponding one of the plurality of electrodes in the first direction.

12. The semiconductor memory device of claim 11 , wherein
a bottom surface of the cell region and a bottom surface of the electrode adjacent to the cell region are at substantially same levels, respectively, and
a top surface of the cell region and a top surface of the electrode adjacent to the cell region are at substantially same levels, respectively.

13. The semiconductor memory device of claim 11 , wherein the charge storage layer comprises a first portion and a remaining portion in the cell region;
wherein the first portion of the charge storage layer of the cell region is in physical contact with the tunnel insulating layer, and
wherein the remaining portion of the charge storage layer of the cell region is spaced apart from the tunnel insulating layer across the filling insulating layer.

14. The semiconductor memory device of claim 11 , wherein the filling insulating layer of the cell separation region is between the charge storage layer and the tunnel insulating layer.

15. The semiconductor memory device of claim 11 , wherein the charge storage layer has a nonlinear shape between a pair of the plurality of electrodes adjacent to each other in a direction normal to the substrate.

16. A semiconductor memory device, comprising:
a stack structure comprising a plurality of electrodes and a plurality of insulating layers that are alternately stacked on a substrate; and
a vertical channel structure penetrating the stack structure,
wherein the vertical channel structure comprises a semiconductor pattern and a vertical insulating layer between the semiconductor pattern and the plurality of electrodes, and
wherein the vertical insulating layer comprises a charge storage layer, a filling insulating layer, and a tunnel insulating layer,
wherein the vertical insulating layer has a cell region between the semiconductor pattern and each of the plurality of electrodes and a cell separation region between the semiconductor pattern and each of the plurality of insulating layers,
wherein a bottom surface of the cell separation region and a bottom surface of the insulating layer adjacent to the cell separation region are at substantially same levels, respectively,
wherein a top surface of the cell separation region and a top surface of the insulating layer adjacent to the cell separation region are at substantially same levels, respectively,
wherein the filling insulating layer of the cell separation region extends from the bottom surface of the cell separation region to the top surface of the cell separation region, and
wherein the filling insulating layer of the cell region overlaps a corresponding one of the plurality of electrodes in a first direction parallel to the substrate.

17. The semiconductor memory device of claim 16 , wherein
the cell region comprises a first cell region and a second cell re

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Sejun
• Lee Jaeduk
• Jang Jaehoon
• Kang Jin-Kyu
• Hong Seungwan
• Hong Okcheon

Classifications

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• H01L27/11582

  Electricity · mapped topic

• H01L27/11556 Primary

  Electricity · mapped topic

• H10D64/516

  the thicknesses being non-uniform · CPC title

• H10D30/694

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title