Display panel with reduced border area improving charging and discharging capacities of gate driving circuit

Patent metadata

Field	Value
Publication number	US-11443709-B2
Application number	US-202117394382-A
Country	US
Kind code	B2
Filing date	Aug 4, 2021
Priority date	Jan 6, 2021
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

A display panel is provided. The display panel includes a plurality of scan lines and a gate driving circuit. The scan lines are disposed on the display panel along a first direction, and respectively provide a plurality of gate driving signals. The gate driving circuit is disposed on a first side of the display panel along a second direction. The second direction intersects the first direction. The gate driving circuit includes a plurality of bias generators and a plurality of signal output circuits. The signal output circuits are divided into a plurality of groups. The bias generators respectively correspond to the groups. The bias generators generate a plurality of first bias voltages. The groups generate the gate driving signals respectively according to the first bias voltages.

First claim

What is claimed is:

1. A display panel, comprising:
a plurality of scan lines arranged on the display panel along a first direction, and respectively providing a plurality of gate driving signals; and
a gate driving circuit arranged on a first side of the display panel along a second direction that intersects the first direction, the gate driving circuit comprising a plurality of bias generators and a plurality of signal output circuits, wherein the plurality of signal output circuits are divided into a plurality of groups, the bias generators respectively correspond to the plurality of groups, the plurality of bias generators generate a plurality of first bias voltages, and the plurality of groups generate the plurality of gate driving signals respectively according to the plurality of first bias voltages,
wherein each of the plurality of bias generators comprises:
a first pull-up circuit pulling up a first control voltage according to a fore-stage bias voltage based on a first voltage;
a second pull-up circuit pulling up a second control voltage according to a first clock signal;
a first pull-down circuit pulling down the first control voltage according to a start signal, the second control voltage and/or a post-stage bias voltage;
a second pull-down circuit pulling down the second control voltage according to the start signal and/or the first control voltage; and
an output stage circuit generating each of the plurality of first bias voltages corresponding to the plurality of groups according to the first control voltage and the second control voltage.

2. The display panel according to claim 1 , wherein
the first pull-up circuit is a pull-up transistor, wherein a first terminal of the pull-up transistor receives the first voltage, and a control terminal of the pull-up transistor receives the fore-stage bias voltage for pulling up the first control voltage on a second terminal of the pull-up transistor;
the second pull-up circuit is a pull-up capacitor, wherein a first terminal of the pull-up capacitor receives the first clock signal for pulling up the second control voltage on a second terminal of the pull-up capacitor;
the first pull-down circuit comprises a plurality of first pull-down transistors, wherein first terminals of the plurality of first pull-down transistors receive the first control voltage, second terminals of the plurality of first pull-down transistors receive a second voltage, and control terminals of the plurality of first pull-down transistors respectively receive the start signal, the second control voltage, and the post-stage bias voltage to pull down the first control voltage;
the second pull-down circuit comprises a plurality of second pull-down transistors, wherein first terminals of the plurality of second pull-down transistors receive the second control voltage, second terminals of the plurality of second pull-down transistors receive the second voltage, and control terminals of the plurality of second pull-down transistors respectively receive the start signal and the first control voltage to pull down the second control voltage; and
the output stage circuit is a buffer, wherein the buffer receives the first clock signal and a third voltage to generate each of the plurality of first bias voltages corresponding to the plurality of groups according to the first control voltage and the second control voltage.

3. The display panel according to claim 1 , wherein each of the plurality of bias generators further provides the second control voltage as a second bias voltage, wherein each of the plurality of signal output circuits in a same group comprises:
a plurality of buffers respectively receiving a plurality of second clock signals, wherein the plurality of buffers respectively generates corresponding gate driving signals according to a first bias voltage and the second bias voltage.

4. The display panel according to claim 1 , wherein each of the plurality of signal output circuits in a same group comprises:
a plurality of buffers respectively receiving a plurality of second clock signals, wherein the plurality of buffers respectively generate corresponding gate driving signals only according to the first bias voltage, and maintain voltage values of the plurality of gate driving signals according to the corresponding gate driving signals and the first bias voltage.

5. The display panel according to claim 1 , wherein each of the plurality of signal output circuits in a same group comprises:
multi-stage voltage generators respectively generating corresponding gate driving signals, wherein each of the multi-stage voltage generators comprises:
a first transistor, wherein a first terminal of the first transistor receives a second clock signal, and a control terminal of the first transistor receives the first bias voltage;
a second transistor, wherein a first terminal of the second transistor is coupled to a second terminal of the first transistor, and a second terminal of the second transistor receives the first bias voltage;
a third transistor and a fourth transistor, wherein first terminals of the third transistor and the fourth transistor are both coupled to a control terminal of the second transistor, second terminals of the third transistor and the fourth transistor both receive a second voltage, a control terminal of the third transistor receives the first bias voltage, and a control terminal of the fourth transistor receives the start signal; and
a capacitor coupled between the first terminal of the first transistor and the control terminal of the second transistor.

6. The display panel according to claim 1 , further comprising:
a first auxiliary circuit arranged on a second side of the display panel along the first direction, wherein the first auxiliary circuit is coupled to the plurality of scan lines for compensating for the plurality of gates driving signals generated by the plurality of signal output circuits.

7. The display panel according to claim 6 , wherein the first auxiliary circuit comprises:
a plurality of first transistors pulling up the plurality of gate driving signals according to a plurality of fore-stage gate driving signals based on a first voltage or a first clock signal.

8. The display panel according to claim 7 , wherein the first auxiliary circuit further comprises:
a plurality of second transistors respectively coupled as a plurality of diodes, wherein the plurality of diodes respectively have a plurality of cathodes respectively coupled to control terminals of the plurality of first transistors, and a plurality of anodes of the plurality of diodes respectively receive the plurality of fore-stage gate driving signals; and
a plurality of capacitors respectively coupled between the control terminals and second terminals of the plurality of first transistors.

9. The display panel according to claim 6 , wherein the first auxiliary circuit comprises:
a plurality of first transistors pulling down the plurality of gate driving signals according to a plurality of post-stage gate driving signals based on a first voltage.

10. The display panel according to claim 6 , wherein the first auxiliary circuit comprises:
multi-stage voltage controllers compensating for the plurality of gate driving signals according to a fore-stage gate driving signal based on a plurality of first clock signals, wherein each of the multi-stage voltage controllers comprises:
a first transistor, wherein a first terminal of the first transistor receives each corresponding gate driving signal;
a second transistor, wherein a second terminal of the second transistor is coupled to a control terminal of the first transistor;
a third transistor and a fourth transistor, wherein

Assignees

• Au Optronics Corp

Inventors

• Tung Che-Wei
• Lin Wei-Li
• Chou Chin-Hsien
• Yeh Yen-Wei

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/3655

  Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title