Semiconductor device

Patent metadata

Field	Value
Publication number	US-10304402-B2
Application number	US-201816199567-A
Country	US
Kind code	B2
Filing date	Nov 26, 2018
Priority date	Sep 9, 2010
Publication date	May 28, 2019
Grant date	May 28, 2019

Abstract

A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.

First claim

What is claimed is:

1. A display device comprising:
a first gate driver circuit;
a second gate driver circuit;
a pixel portion between the first gate driver circuit and the second gate driver circuit; and
a gate line electrically connected to the first gate driver circuit and the second gate driver circuit,
wherein the first gate driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor,
wherein the second gate driver circuit comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the first transistor is electrically connected to the gate line,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein the one of the source and the drain of the fifth transistor is electrically connected to a gate of the third transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to a third wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fifth transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the fifth transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein a gate of the first transistor is electrically connected to a gate of the fourth transistor,
wherein the gate of the first transistor is electrically connected to a gate of the sixth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor,
wherein the one of the source and the drain of the seventh transistor is electrically connected to the gate line,
wherein one of a source and a drain of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor,
wherein the one of the source and the drain of the ninth transistor is electrically connected to a gate of the eighth transistor,
wherein one of a source and a drain of the eleventh transistor is electrically connected to one of a source and a drain of the twelfth transistor,
wherein the one of the source and the drain of the eleventh transistor is electrically connected to a gate of the ninth transistor,
wherein the other of the source and the drain of the seventh transistor is electrically connected to a fourth wiring,
wherein the other of the source and the drain of the eighth transistor is electrically connected to a fifth wiring,
wherein the other of the source and the drain of the ninth transistor is electrically connected to a sixth wiring,
wherein the other of the source and the drain of the ninth transistor is electrically connected to the other of the source and the drain of the eleventh transistor,
wherein the other of the source and the drain of the ninth transistor is electrically connected to a gate of the eleventh transistor,
wherein the other of the source and the drain of the tenth transistor is electrically connected to the other of the source and the drain of the twelfth transistor,
wherein a gate of the seventh transistor is electrically connected to a gate of the tenth transistor,
wherein the gate of the seventh transistor is electrically connected to a gate of the twelfth transistor,
wherein a first signal is input to the third wiring,
wherein a second signal different from the first signal is input to the sixth wiring,
wherein a third signal is input to each of the first wiring and the fourth wiring,
wherein a first frame includes a first period during which the first transistor is turned on, and
wherein the seventh transistor is turned on in the first period.

2. The display device according to claim 1 , wherein the first wiring is electrically connected to the fourth wiring.

3. The display device according to claim 2 , wherein the second wiring is electrically connected to the fifth wiring.

4. The display device according to claim 1 , wherein the second wiring is electrically connected to the fifth wiring.

5. A display device comprising:
a first gate driver circuit;
a second gate driver circuit;
a pixel portion between the first gate driver circuit and the second gate driver circuit; and
a gate line electrically connected to the first gate driver circuit and the second gate driver circuit,
wherein the first gate driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor,
wherein the second gate driver circuit comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the first transistor is electrically connected to the gate line,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the one of the source and the drain of the third transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,
wherein the one of the source and the drain of the fifth transistor is electrically connected to a gate of the third transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to a third wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the fifth transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the fifth transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the sixth transistor,
wherein a gate of the first transistor is electrically connected to a gate of the fourth transistor,
wherein the gate of the first transistor is electrically connected to a gate of the sixth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor,
wherein the one of the source and the drain of the seventh transistor is electrically connected to the gate line,
wherein one of a source and a dra

Assignees

• Semiconductor Energy Lab

Inventors

• Kimura Hajime
• Umezaki Atsushi

Classifications

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/3688

  suitable for active matrices only · CPC title

• G09G2320/043

  Preventing or counteracting the effects of ageing · CPC title

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title