Semiconductor device

Patent metadata

Field	Value
Publication number	US-10140942-B2
Application number	US-201815995210-A
Country	US
Kind code	B2
Filing date	Jun 1, 2018
Priority date	Sep 9, 2010
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.

First claim

What is claimed is:

1. A display device comprising:
a first gate driver circuit;
a second gate driver circuit; and
a pixel portion between the first gate driver circuit and the second gate driver circuit,
wherein the first gate driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor,
wherein the second gate driver circuit comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one end of a gate signal line,
wherein one of a source and a drain of the second transistor is electrically connected to the one end of the gate signal line,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a gate of the fourth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the second transistor,
wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fifth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the other end of the gate signal line,
wherein one of a source and a drain of the eighth transistor is electrically connected to the other end of the gate signal line,
wherein one of a source and a drain of the ninth transistor is electrically connected to a gate of the seventh transistor,
wherein one of a source and a drain of the tenth transistor is electrically connected to the gate of the eighth transistor,
wherein the other of the source and the drain of the tenth transistor is electrically connected to a gate of the tenth transistor,
wherein one of a source and a drain of the eleventh transistor is electrically connected to the gate of the eighth transistor,
wherein a gate of the eleventh transistor is electrically connected to the gate of the seventh transistor,
wherein one of a source and a drain of the twelfth transistor is electrically connected to the gate of the seventh transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the eleventh transistor,
wherein a clock signal is input to the other of the source and the drain of the first transistor,
wherein a start signal is input to a gate of the third transistor,
wherein a first potential is input to the other of the source and the drain of the fourth transistor during a frame period,
wherein a second potential is input to the other of the source and the drain of the fourth transistor during another frame period, and
wherein the second potential is higher than the first potential.

2. The display device according to claim 1 , wherein a reset signal is input to a gate of the sixth transistor.

3. The display device according to claim 1 , wherein the gate of the third transistor is electrically connected to the other of the source and the drain of the third transistor.

4. The display device according to claim 1 , wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor is an N-channel type transistor.

5. A display device comprising:
a first gate driver circuit;
a second gate driver circuit; and
a pixel portion between the first gate driver circuit and the second gate driver circuit,
wherein the first gate driver circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor,
wherein the second gate driver circuit comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one end of a gate signal line,
wherein one of a source and a drain of the second transistor is electrically connected to the one end of the gate signal line,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to a gate of the second transistor,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a gate of the fourth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the second transistor,
wherein a gate of the fifth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fifth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the other end of the gate signal line,
wherein one of a source and a drain of the eighth transistor is electrically connected to the other end of the gate signal line,
wherein one of a source and a drain of the ninth transistor is electrically connected to a gate of the seventh transistor,
wherein one of a source and a drain of the tenth transistor is electrically connected to the gate of the eighth transistor,
wherein the other of the source and the drain of the tenth transistor is electrically connected to a gate of the tenth transistor,
wherein one of a source and a drain of the eleventh transistor is electrically connected to the gate of the eighth transistor,
wherein a gate of the eleventh transistor is electrically connected to the gate of the seventh transistor,
wherein one of a source and a drain of the twelfth transistor is electrically connected to the gate of the seventh transistor,
wherein the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the eleventh transistor,
wherein a clock signal is input to the other of the source and the drain of the first transistor,
wherein a start signal is input to a gate of the third transistor,
wherein a first potential is input to the other of the source and the drain of the fourth transistor from when the first transistor is turned on in a first frame period until the first transistor is turned off in the first frame period,
wherein a second potential is input to the other of the source and the drain of the fourth transistor from when the first transistor is turned on in a second frame period until the first transistor is turned off in the second frame period, and
wherein the second potential is higher than the first potential.

6. The display device according to claim 5 , wherein a reset signal is input to a gate of the sixth transistor.

7. The display device according to claim 5 , wherein the gate of the third

Assignees

• Semiconductor Energy Lab

Inventors

• Kimura Hajime
• Umezaki Atsushi

Classifications

• G09G2320/0209

  Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display · CPC title

• G09G2320/0223

  Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2320/043

  Preventing or counteracting the effects of ageing · CPC title