Error detection code generation circuits of semiconductor devices, memory controllers including the same and semiconductor memory devices including the same

Patent metadata

Field	Value
Publication number	US-11438016-B2
Application number	US-202017110777-A
Country	US
Kind code	B2
Filing date	Dec 3, 2020
Priority date	Dec 2, 2016
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.

First claim

What is claimed is:

1. A memory system performing an error detecting operation, the memory system comprising:
a semiconductor memory device configured to perform the error detecting operation in a full code rate mode in response to a first level of a mode signal and in a half code rate mode in response to a second level of the mode signal respectively; and
a memory controller coupled to the semiconductor memory device, the memory controller configured to:
transmit first and second unit data and first and second data bus inversion bits to the semiconductor memory device;
generate final error detection code bits based on the first and second unit data and the first and second data bus inversion bits;
receive return error detection code bits from the semiconductor memory device, the return error detection code bits comprising first and second error detection code bits during the full code rate mode and merged error detection code bits during the half code rate mode; and
compare the final error detection code bits and the return error detection code bits to determine whether the first and second unit data and the first and second data bus inversion bits received by the semiconductor include an error,

wherein the return error detection code bits are generated by an error detection code generation circuit, and the error detection code generation circuit comprises:
a first cyclic redundancy check (CRC) engine configured to receive the first unit data and the first data bus inversion bits and to generate the first error detection code bits based on the first unit data and the first data bus inversion bits;
a second CRC engine configured to receive second unit data and second data bus inversion bits and to generate the second error detection code bits based on the second unit data and the second data bus inversion bits, the second error detection code bits including a selected bit and remaining unselected bits, the selected bit of the second error detection code bits having a first value during the full code rate mode and having a second value during the half code rate mode, and the remaining unselected bits of the second error detection code bits have same values during the full code rate mode and the half code rate mode; and
an XOR circuit configured to receive the first error detection code bits and the second error detection code bits and to output the merged error detection code bits by performing an exclusive OR function during the half code rate mode, and

wherein the error detection code generation circuit is configured to output the first error detection code bits and the second error detection code bits in response to the first level of the mode signal and to output the merged error detection code bits in response to the second level of the mode signal.

2. The memory system of claim 1 , wherein the selected bit is the most significant bit of the second error detection code bits.

3. The memory system of claim 1 , wherein the memory controller is further configured to retransmit the first and second unit data and first and second data bus inversion bits when the comparison result indicates a mismatch between the final error detection code bits and the return error detection code bits.

4. The memory system of claim 1 , wherein the memory controller is configured to compare the final error detection code bits with the first and second error detection code bits during the full code rate mode and with die merged error detection code bits during the half code rate mode respectively.

5. The memory system of claim 1 , wherein the memory controller includes a CRC generator configured to receive the first and second unit data and the first and second data bus inversion bits and to generate the final error detection code bits and a CRC checker configured to compare the final error detection code bits with the return error detection code bits.

6. The memory system of claim 5 , wherein the CRC generator comprises:
a first buffer to store the final error detection code bits;
a second buffer to store the return final error detection code bits;
a comparator connected to the first buffer and the second buffer, the comparator configured to compare corresponding bits of the final error detection code bits and the return final error detection code bits to determine whether each corresponding bits of the final error detection code bits and the return final error detection code bits matches each other.

7. The memory system of claim 1 , wherein the second CRC engine includes a multiplexer configured to output the first value of the selected bit in response to the first level of the mode signal and the second value of the selected bit in response to the second level of the mode signal.

8. The memory system of claim 1 , wherein the first error detection code bits are generated by applying a first generation matrix on the first unit data and the first data bus inversion bits, and the second error detection code bits are generated by applying a second generation matrix on the second unit data and the second data bus inversion bits, the second generation matrix includes first matrix elements corresponding to the selected bit of the second error detection code bits and second matrix elements corresponding to remaining unselected bits of the second error detection code bits, and the first matrix elements of the second generation matrix, during the full code rate mode, has a first data pattern in response to the first level of the mode signal, and during the half code rate mode, has a second data pattern in response to the second level of the mode signal, the first and second data patterns being inverted patterns from each other.

9. The memory system of claim 8 , wherein, during the half code rate mode, the first matrix elements of the second generation matrix and corresponding matrix elements of the first generation matrix are inverted with respect to each other.

10. An error detection code generation circuit comprising:
a first cyclic redundancy check (CRC) engine configured to receive the first unit data and the first data bus inversion bits and to generate first error detection code bits based on the first unit data and the first data bus inversion bits;
a second CRC engine configured to receive second unit data and second data bus inversion bits and to generate second error detection code bits based on the second unit data and the second data bus inversion bits, the second error detection code bits including a selected bit and remaining unselected bits, the selected bit of the second error detection code bits having a first bit value during the full code rate mode and having a second bit value during the half code rate mode, and the remaining unselected bits of the second error detection code bits have same values regardless of the code rate modes; and
an XOR circuit configured to receive the first error detection code bits and the second error detection code bits and to output the merged error detection code bits by performing an exclusive OR function during the half code rate mode,
wherein the error detection code generation circuit is configured to output the first error detection code bits and the second error detection code bits in response to the first level of the mode signal and to output the merged error detection code bits in response to the second level of the mode signal,
wherein the first error detection code bits are generated by applying a first generation matrix on the first unit data and the first data bus inversion bits, and the second error detection code bits are generated by applying a second generation matrix on the second unit data and the second data bus inversion bits, the second generation matrix includes first

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cha Sang-Uhn
• Ryu Ye-Sin
• Kim Young-Sik
• Doo Su-Yeon

Classifications

• H03M13/09

  Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit · CPC title

• H03M13/2906 Primary

  using block codes (H03M13/2957 takes precedence) · CPC title

• G06F11/102 Primary

  Error in check bits · CPC title

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title