Memory controller and method of data bus inversion using an error detection correction code

Patent metadata

Field	Value
Publication number	US-2016173128-A1
Application number	US-201514941564-A
Country	US
Kind code	A1
Filing date	Nov 14, 2015
Priority date	Dec 10, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

First claim

We claim:

1 . A memory controller comprising:
write circuitry to transmit write data along a databus to a memory device, the write circuitry including:
a write error detection correction (EDC) encoder to generate first error information associated with the write data, and
data bus inversion (DBI) circuitry to conditionally invert data bits associated with each of the write data words based on threshold criteria; and
read circuitry to receive read data from the memory device, the read data corresponding to the write data words, the read circuitry including
a read EDC encoder to generate second error information associated with the received read data, and
logic to evaluate the first and second error information, and conditionally reverse-invert at least a portion of the read data based on the evaluating.

2 . The memory controller according to claim 1 , wherein the logic is operative to conditionally reverse-invert at least a portion of the decoded bits based on a comparison of a write data syndrome generated from the first error information to a read data syndrome generated from the second error information.

3 . The memory controller according to claim 1 , wherein the logic is operative to conditionally reverse-invert at least a portion of the decoded bits based on a comparison of a write data syndrome generated from the first error information to a more likely read data syndrome generated from the second error information.

4 . The memory controller according to claim 1 , wherein:
the DBI circuitry conditionally inverts data bits including the EDC code for each write data word.

5 . The memory controller according to claim 1 , wherein:
the DBI circuitry conditionally inverts data bits including each write data word.

6 . The memory controller according to claim 1 , wherein:
the DBI circuitry is operative to conditionally invert data bits based on a population count.

7 . The memory controller according to claim 1 , wherein:
the symbol-based EDC code includes symbols that each have a group of four data bits.

8 . The memory controller according to claim 1 , wherein:
the EDC code is to correct a first class of errors.

9 . The memory controller according to claim 1 , wherein:
the EDC code is to detect a second class of errors.

10 . The memory controller according to claim 1 , embodied as a dynamic random access (DRAM) memory controller.

11 . The memory controller according to claim 1 , wherein the databus is 144-bits wide.

12 . A method of controlling write and read accesses between a memory controller and a memory device, the method comprising:
processing write transactions to the memory device by
generating a symbol-based EDC code for each of multiple write data words associated with write data, and
conditionally inverting data bits associated with each of the write data words based on threshold criteria; and
processing received read data from the memory device by
generating read data error information from the received read data, and
conditionally reverse-inverting at least a portion of the read data based on the read data error information.

13 . The method of claim 12 , wherein:
the conditionally reverse-inverting at least a portion of the received read data is based on a comparison of write data error information associated with the symbol-based EDC code to the read data error information.

14 . The method of claim 12 , wherein:
the conditionally reverse-inverting at least a portion of the received read data is based on a comparison of write data error information associated with the symbol-based EDC code to a most likely version of the read data error information.

15 . The method of claim 12 , wherein:
the conditionally inverting data bits includes conditionally inverting the EDC code for each write data word.

16 . The method of claim 12 , wherein:
conditionally inverting data bits includes conditionally inverting each write data word.

17 . The method of claim 12 , wherein:
conditionally inverting data bits includes conditionally inverting data bits based on a population count.

18 . The method of claim 12 , wherein:
the EDC code is to correct a first class of errors or detect a second class of errors.

19 . A method comprising:
receiving read data symbols from a memory device; EDC encoding the read data symbols to generate a read data error syndrome; comparing the read data error syndrome to a write data syndrome associated with the read data symbols, the comparing to generate a signature; and selectively inverting the read data symbols based on the signature.

20 . The method according to claim 19 , further comprising:
generating the write data syndrome during a write transaction to the memory device; transferring the write data syndrome to the memory device during a write transaction; and receiving the write data syndrome from the memory device during a read transaction involving the read data symbols.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Linstadt John Eric

Classifications

• H03M13/19

  Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes · CPC title

• G06F3/0673

  Single storage device · CPC title

• H03M13/05 Primary

  using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits {(H03M13/2906 takes precedence)} · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F11/1016

  Error in accessing a memory location, i.e. addressing error · CPC title