Three-dimensional semiconductor memory devices

Patent metadata

Field	Value
Publication number	US-11437397-B2
Application number	US-201816139775-A
Country	US
Kind code	B2
Filing date	Sep 24, 2018
Priority date	Feb 7, 2018
Publication date	Sep 6, 2022
Grant date	Sep 6, 2022

Abstract

A three-dimensional (3D) semiconductor memory device includes a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate, and an electrode structure including an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction perpendicular to the top surface of the substrate.

First claim

What is claimed is:

1. A three-dimensional (3D) semiconductor memory device, comprising:
a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate; and
an electrode structure comprising an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction that is perpendicular to the top surface of the substrate,
wherein a first maximum thickness in the first direction of the erase control gate electrode is greater than a second maximum thickness in the first direction of the ground selection gate electrode.

2. The 3D semiconductor memory device of claim 1 , wherein a first distance between the ground selection gate electrode and a cell gate electrode of the cell gate electrodes that is closest to the substrate is greater than a second distance between the erase control gate electrode and the ground selection gate electrode, and wherein the first distance is greater than a third distance between adjacent ones of the cell gate electrodes.

3. The 3D semiconductor memory device of claim 1 , further comprising:
a vertical semiconductor pattern that extends in the first direction, wherein the source conductive pattern is in contact with a portion of a sidewall of the vertical semiconductor pattern,
wherein the source conductive pattern comprises:
a horizontal portion extending in parallel to the electrode structure under the electrode structure; and
a sidewall portion extending from the horizontal portion in the first direction and surrounding the portion of the sidewall of the vertical semiconductor pattern.

4. The 3D semiconductor memory device of claim 3 , further comprising:
a data storage pattern extending in the first direction between the vertical semiconductor pattern and the electrode structure,
wherein a bottom surface of the data storage pattern is in contact with the sidewall portion of the source conductive pattern.

5. The 3D semiconductor memory device of claim 4 , wherein the data storage pattern has a first thickness on the sidewall of the vertical semiconductor pattern,
wherein the sidewall portion of the source conductive pattern has a second thickness on the sidewall of the vertical semiconductor pattern, and
wherein the second thickness of the sidewall portion of the source conductive pattern is equal to the first thickness of the data storage pattern.

6. The 3D semiconductor memory device of claim 4 , further comprising:
a dummy data storage pattern between the substrate and the vertical semiconductor pattern and spaced apart from the data storage pattern with the source conductive pattern interposed therebetween,
wherein a surface of the dummy data storage pattern is located at a level between the top surface of the substrate and a bottom surface of the substrate.

7. The 3D semiconductor memory device of claim 1 , wherein the source conductive pattern comprises:
a first source conductive pattern on the substrate; and
a second source conductive pattern in contact with a top surface of the first source conductive pattern,
wherein the first source conductive pattern and the second source conductive pattern comprise a semiconductor material doped with n-type dopants, and
wherein a first concentration of the n-type dopants in the first source conductive pattern is greater than a second concentration of the n-type dopants in the second source conductive pattern.

8. The 3D semiconductor memory device of claim 7 , wherein the second source conductive pattern extends from the top surface of the first source conductive pattern onto a portion of a recessed sidewall of the first source conductive pattern that is recessed in a second direction that is orthogonal to the first direction.

9. The 3D semiconductor memory device of claim 1 , further comprising:
a vertical semiconductor pattern which extends in the first direction, wherein the source conductive pattern is in contact with a portion of a sidewall of the vertical semiconductor pattern; and
a source contact plug spaced apart from the vertical semiconductor pattern and penetrating the electrode structure, wherein the source contact plug is connected to the source conductive pattern.

10. The 3D semiconductor memory device of claim 1 , wherein the source conductive pattern comprises:
a first source conductive pattern on the substrate; and
a second source conductive pattern in contact with a top surface of the first source conductive pattern;
wherein the first source conductive pattern comprises:
a horizontal portion extending in parallel to the electrode structure under the electrode structure; and
a sidewall portion extending from the horizontal portion in the first direction and surrounding the portion of the sidewall of the vertical semiconductor pattern, and
wherein a top surface of the sidewall portion of the first source conductive pattern is located at a level higher than a top surface of the second source conductive pattern.

11. A three-dimensional (3D) semiconductor memory device, comprising:
an n-type source conductive pattern extending in parallel to a top surface of a substrate; and
a plurality of NAND cell strings provided on the n-type source conductive pattern and extending in a first direction perpendicular to the top surface of the substrate, wherein each of the plurality of NAND cell strings comprises:
a cell string comprising a plurality of memory cell transistors connected in series to each other;
a ground selection transistor connected to a first end of the cell string; and
an erase control transistor connected between the ground selection transistor and the n-type source conductive pattern,
wherein a maximum thickness of a first gate electrode of the erase control transistor is greater than a maximum thickness of a second gate of the ground selection transistor in the first direction,
wherein the n-type source conductive pattern comprises:
a first source conductive pattern on the substrate; and
a second source conductive pattern in contact with a top surface of the first source conductive pattern,

wherein the first source conductive pattern and the second source conductive pattern each comprise a semiconductor material doped with n-type dopants, and
wherein a first concentration of the n-type dopants in the first source conductive pattern is greater than a second concentration of the n-type dopants in the second source conductive pattern.

12. The 3D semiconductor memory device of claim 11 , wherein each of the plurality of NAND cell strings further comprises a string selection transistor connected to a second end of the cell string.

13. The 3D semiconductor memory device of claim 11 , further comprising:
an erase control line, a ground selection line, and a plurality of word lines, which are sequentially stacked on the n-type source conductive pattern in the first direction with insulating layers interposed between respective ones of the erase control line, the ground selection line, and the plurality of word lines,
wherein the erase control line is connected to the first gate electrode of the erase control transistor, wherein the ground selection line is connected to the second gate electrode of the ground selection transistor, and
wherein the plurality of word lines are connected to third gate electrodes of the plurality of memory cell transistors, respectively.

14. The 3D semiconductor memory device of claim 11 , wherein the n-type source conductive pattern comprises poly-silicon doped with n-type dopants.

Assignees

• Samsung Electronics Co Ltd

Inventors

• JUNG Euntaek
• Shin Joongshik
• Hong Sangjun

Classifications

• H10D30/696

  having at least one additional gate, e.g. program gate, erase gate or select gate · CPC title

• H01L27/1157

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic