Three dimensional NAND memory having improved connection between source line and in-hole channel material as well as reduced damage to in-hole layers

Patent metadata

Field	Value
Publication number	US-9711532-B2
Application number	US-201615292898-A
Country	US
Kind code	B2
Filing date	Oct 13, 2016
Priority date	Dec 22, 2014
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without exposing a programmable material lining of an interior sidewall of the memory hole and without exposing a channel forming region also lining an interior of the memory hole to an energetic and potentially damaging etch environment. The stack includes alternating control gate layers and dielectric layers on a substrate, and the memory hole is etched through the stack before lining an interior sidewall thereof with the programmable material and then with the channel forming material. The process avoids a need to energetically etch down through the memory hole to open up a source contact hole near the bottom of the channel forming material by instead etching upwardly from beneath the memory hole.

First claim

What is claimed is:

1. A three-dimensional stacked non-volatile memory device, comprising:
a first memory hole defined as extending vertically at least from a top of and through a stack of alternating word line layers and dielectric layers, the first memory hole having a vertically extending interior coated with a layer of programmable material having a first thickness and with a more interior layer of channel forming material having a second thickness, the channel forming material being one of an undoped semiconductive material and a lightly doped semiconductive material of a first conductivity type;
a source region disposed at an underneath portion of the channel forming material and having a second conductivity type opposite to said first conductivity type, the underneath portion of the channel forming material being disposed at and extending horizontally parallel with a bottom of the first memory hole; and
a horizontally extending layer of the programmable material continuing from the programmable material coating the vertically extending interior of the first memory hole and being disposed underneath the alternating word line and dielectric layers.

2. The memory device of claim 1 wherein:
the programmable material that coats a sidewall of the interior of the first memory hole is one that is not damaged by having been subjected to an etching environment after the programmable material is formed to coat the sidewall of the interior of the first memory hole.

3. The memory device of claim 2 wherein the source region includes a heavily doped semiconductor making contact with the horizontally extending layer of the programmable material.

4. The memory device of claim 1 and further comprising:
a horizontally extending layer of metal disposed under and making electrical connection with the source region.

5. The memory device of claim 1 wherein:
the first memory hole is filled at a yet more interior portion of thereof with a dielectric support material, the yet more interior portion being interior of the layer of channel forming material.

6. The memory device of claim 5 wherein:
the dielectric support material includes a silicon oxide.

7. The memory device of claim 5 wherein:
the programmable material extends to be disposed at locations below a lowest level of the dielectric support material.

8. The memory device of claim 7 wherein:
a horizontally extending portion of the channel forming material is interposed between the source region and the dielectric support material.

9. The memory device of claim 5 wherein:
the horizontally extending portion of the channel forming material underlies the dielectric support material.

10. The memory device of claim 1 and further comprising:
a horizontally extending layer of heavily doped semiconductor forming part of the source region and making contact with the horizontally extending portion of the channel forming material; and
a horizontally extending layer of metallic interconnect making contact with the horizontally extending layer of heavily doped semiconductor.

11. The memory device of claim 10 and further comprising:
a vertically extending layer of metallic interconnect continuing from the horizontally extending layer of metallic interconnect.

12. The memory device of claim 1 and further comprising:
a horizontally extending layer of heavily doped semiconductor forming part of the source regions and making contact with the horizontally extending portion of the channel forming material; and
a vertically extending layer of metallic interconnect making contact with the horizontally extending layer of heavily doped semiconductor.

13. The memory device of claim 1 and further comprising:
a second memory hole defined as extending through the stack of alternating word line layers and dielectric layers, the second memory hole having a respective second interior coated with a respective second layer of the programmable material having the first thickness and with a respective second more interior layer of the channel forming material having the second thickness;
a second source region disposed at respective second underneath portion of the channel forming material of the second memory hole, the respective second underneath portion being disposed at the bottom of the second memory hole; and
a respective second horizontally extending layer of the programmable material continuing from the programmable material coating the interior of the second memory hole and being disposed under the stack of alternating word line and dielectric layers.

14. The memory device of claim 13 wherein:
the second source region of the second memory hole is contiguous with source region of the first memory hole.

15. The memory device of claim 13 and further comprising:
a metal filled source trench extending adjacent to and connected to the second source region of the second memory hole and to the source region of the first memory hole.

16. The memory device of claim 1 and further comprising:
a source region contacting conductor extending from at least a top of the stack, through the stack and further extending to make contact with the source region.

Assignees

• Sandisk Technologies Llc

Inventors

• Miyamoto Masato
• Fukano Yuji

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/418

  the conductive layers comprising transition metals · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H01L21/28568

  Electricity · mapped topic