Resistive random access memory device

Patent metadata

Field	Value
Publication number	US-11430953-B2
Application number	US-202117140495-A
Country	US
Kind code	B2
Filing date	Jan 4, 2021
Priority date	Feb 28, 2018
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.

First claim

What is claimed is:

1. A method of making a memory cell, comprising:
forming a trench over a dielectric layer;
forming a first contact feature in the trench;
forming a first barrier layer that completely surrounds and directly contacts top, bottom and side surfaces of the first contact feature;
forming a resistive material layer over the first contact feature;
forming a second contact feature over the resistive material layer; and
forming a second barrier layer that completely surrounds and directly contacts top, bottom and side surfaces of the second contact feature.

2. The method of claim 1 , wherein the first barrier layer comprises a first portion disposed in the dielectric layer and extending along a lower boundary and sidewalls of the first contact feature, and a second portion disposed above the dielectric layer and extending along an upper boundary of the first contact feature.

3. The method of claim 1 , further comprising:
providing a substrate;
forming source/drain features of a transistor in the substrate; and
forming a gate of the transistor in the dielectric layer, wherein the dielectric layer is formed over the substrate.

4. The method of claim 3 , further comprising forming a contact plug extending from a top surface of the dielectric layer to a top surface of the substrate, wherein the contact plug is coupled to at least one of source/drain features.

5. The method of claim 1 , wherein forming the first contact feature comprises:
filling the trench with a metal material; and
polishing excessive metal material until an upper boundary of the first contact feature is exposed.

6. The method of claim 1 , further comprising forming a first capping material layer over the first contact features, wherein the resistive material layer is formed over the first capping material layer.

7. The method of claim 6 , further comprising forming a second capping material layer over the resistive material layer.

8. The method of claim 7 , wherein the resistive material layer comprises a variable resistive material.

9. A method of manufacturing a memory cell, the method comprising:
providing a substrate;
forming a source/drain feature of a transistor in the substrate;
forming a first dielectric layer over the substrate;
forming a gate of the transistor in the first dielectric layer;
forming a second dielectric layer over the first dielectric layer;
forming a first contact feature in the second dielectric layer;
forming a first barrier layer that completely surrounds and directly contacts top, bottom and side surfaces of the first contact feature;
forming a resistive material layer disposed above the first contact feature;
forming a second contact feature disposed above the resistive material layer;
forming a second barrier layer that completely surrounds and directly contacts top, bottom and side surfaces of the second contact feature; and
forming a conductive plug within the first dielectric layer, wherein the conductive plug electrically couples the first contact feature to the source/drain feature.

10. The method of claim 9 , wherein the resistive material layer presents a variable resistance value.

11. The method of claim 9 , wherein at least one of the first and second contact features is partially embedded in a low-k dielectric layer.

12. The method of claim 11 , wherein the first barrier layer comprises a first portion disposed between the low-k dielectric layer and the first contact feature.

13. The method of claim 12 , wherein the first portion of the first barrier layer extends along a top boundary, a lower boundary and sidewalls of the first contact feature.

14. The method of claim 11 , wherein the first barrier layer comprises a second portion disposed above the low-k dielectric layer.

15. The method of claim 14 , wherein the second portion of the first barrier layer is formed as a thin film that fully overlays an upper boundary of the first contact feature.

16. A method of manufacturing a memory cell, the method comprising:
providing a substrate;
forming a source/drain feature of a transistor in the substrate;
forming a first dielectric layer over the substrate;
forming a first contact feature at least partially embedded in the first dielectric layer;
forming a first barrier layer that completely surrounds and directly contacts top, bottom and side surfaces of the first contact feature, the first barrier layer comprising a first portion disposed between the first contact feature and the first dielectric layer, and a second portion disposed above the first dielectric layer;
forming a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer;
forming a second contact feature embedded in a second dielectric layer above the first dielectric layer; and
forming a second barrier layer that completely surrounds and directly contacts top, bottom and side surfaces of the second contact feature; and
forming a conductive plug in the first dielectric layer, the conductive plug electrically coupling the first contact feature to the source/drain feature.

17. The method of claim 16 , wherein the resistive material layer presents a variable resistance value.

18. The method of claim 16 , wherein the first and second dielectric layers are each formed of a low-k dielectric material.

19. The method of claim 16 , wherein the first portion of the first barrier layer extends along a lower boundary and sidewalls of the first contact feature.

20. The method of claim 16 , the second portion of the first barrier layer fully overlays an upper boundary of the first contact feature.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Huei-Tsz
• Wang Po-Shu
• Wang Wei-Ming

Classifications

• H10W46/301

  for alignment · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title