Bottom electrode for RRAM structure

Patent metadata

Field	Value
Publication number	US-10109793-B2
Application number	US-201615275554-A
Country	US
Kind code	B2
Filing date	Sep 26, 2016
Priority date	Nov 13, 2015
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

The present disclosure relates to a memory cell having a multi-layer bottom electrode with an insulating core that provides for good gap fill ability, and an associated method of formation. In some embodiments, the memory cell includes a bottom electrode having an insulating material surrounded by a conductive material. A dielectric data storage layer is arranged over the bottom electrode, and a top electrode is arranged over the dielectric data storage layer.

First claim

What is claimed is:

1. A memory cell, comprising:
a bottom electrode comprising an insulating material completely surrounded by one or more conductive materials;
a data storage layer arranged over the bottom electrode; and
a top electrode arranged over the data storage layer.

2. The memory cell of claim 1 , wherein the insulating material is arranged laterally between sidewalls of a conductive lower bottom electrode layer and vertically between the conductive lower bottom electrode layer and a conductive upper bottom electrode layer.

3. The memory cell of claim 2 , wherein the conductive upper bottom electrode layer extends past outermost sidewalls of the insulating material.

4. The memory cell of claim 2 , wherein the insulating material has an upper surface that is substantially co-planar with an upper surface of the conductive lower bottom electrode layer.

5. The memory cell of claim 2 , wherein the conductive lower bottom electrode layer comprises a ‘U’ shaped layer having a cavity arranged within a top surface of the conductive lower bottom electrode layer, and the insulating material is confined to within the cavity.

6. The memory cell of claim 2 , wherein the bottom electrode further comprises an additional conductive lower bottom electrode layer arranged laterally and vertically between the conductive lower bottom electrode layer and the insulating material.

7. The memory cell of claim 6 , wherein the conductive lower bottom electrode layer has a smaller thickness than the additional conductive lower bottom electrode layer.

8. The memory cell of claim 6 , wherein the conductive lower bottom electrode layer comprises tantalum nitride and the additional conductive lower bottom electrode layer comprises titanium nitride.

9. The memory cell of claim 1 , further comprising:
a lower insulating layer laterally surrounding a lower part of the bottom electrode, wherein the lower insulating layer has an uppermost surface that is below an uppermost surface of the bottom electrode.

10. The memory cell of claim 9 , wherein the bottom electrode has a lower surface that is directly over the lower insulating layer.

11. The memory cell of claim 1 ,
wherein the one or more conductive materials comprise a first conductive material and a second conductive material; and
wherein the second conductive material is disposed over the first conductive material.

12. A memory cell, comprising:
a multi-layer bottom electrode comprising an insulating bottom electrode layer arranged laterally between sidewalls of a conductive lower bottom electrode layer and vertically between the conductive lower bottom electrode layer and a conductive upper bottom electrode layer;
a data storage layer arranged over the multi-layer bottom electrode and configured to store a data state; and
a top electrode arranged over the data storage layer.

13. The memory cell of claim 12 , wherein the conductive lower bottom electrode layer comprises a ‘U’ shaped layer having a cavity arranged within a top surface of the conductive lower bottom electrode layer, and the insulating bottom electrode layer is arranged within the cavity.

14. The memory cell of claim 12 , further comprising:
a conductive second lower bottom electrode layer laterally and vertically arranged between the insulating bottom electrode layer and the conductive lower bottom electrode layer.

15. The memory cell of claim 12 , further comprising:
a lower insulating layer arranged over a lower metal interconnect layer surrounded by a lower inter-level dielectric layer; and
wherein the multi-layer bottom electrode is arranged within an opening vertically extending through the lower insulating layer.

16. The memory cell of claim 15 , wherein the insulating bottom electrode layer comprises a same material as the lower insulating layer.

17. A memory cell, comprising:
a first electrode, comprising:
a first conductive layer having exterior sidewalls and interior sidewalls, wherein the interior sidewalls define a recess within the first conductive layer;
an insulating layer arranged over the first conductive layer and between the interior sidewalls; and
a second conductive layer on the first conductive layer and the insulating layer;

a second electrode comprising a third conductive layer; and
a data storage element arranged between the first electrode and the second electrode, wherein the data storage element is configured to store a data state.

18. The memory cell of claim 17 , wherein the insulating layer completely fills the recess within the first conductive layer.

19. The memory cell of claim 17 , wherein the second conductive layer directly contacts the first conductive layer.

20. The memory cell of claim 17 , wherein the first conductive layer and the second conductive layer completely surround the insulating layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Jen-Sheng
• Chu Wen-Ting
• Liao yu-wen

Classifications

• H01L45/1675

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic

• H01L27/2481

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L45/14

  Electricity · mapped topic