Capacitive microelectromechanical device and method for forming a capacitive microelectromechanical device

Patent metadata

Field	Value
Publication number	US-11422151-B2
Application number	US-202016860528-A
Country	US
Kind code	B2
Filing date	Apr 28, 2020
Priority date	Jul 7, 2015
Publication date	Aug 23, 2022
Grant date	Aug 23, 2022

Abstract

A capacitive microelectromechanical device is provided. The capacitive microelectromechanical device includes a semiconductor substrate, a support structure, an electrode element, a spring element, and a seismic mass. The support structure, for example, a pole, suspension or a post, is fixedly connected to the semiconductor substrate, which may comprise silicon. The electrode element is fixedly connected to the support structure. Moreover, the seismic mass is connected over the spring element to the support structure so that the seismic mass is displaceable, deflectable or movable with respect to the electrode element. Moreover, the seismic mass and the electrode element form a capacitor having a capacitance which depends on a displacement between the seismic mass and the electrode element.

First claim

What is claimed is:

1. A method for forming a capacitive microelectromechanical device, the method comprising:
providing a semiconductor substrate comprising a base portion and sidewall portions that extend from the base portion, wherein a recess is defined by the base portion and the sidewall portions;
forming a support structure fixedly connected to the substrate and arranged within the recess, wherein the support structure comprises a first end and a second end located opposite to the first end, wherein the first end of the support structure is fixedly connected directly to the base portion of the semiconductor substrate, wherein the support structure extends from the first end to the second end in a direction parallel to the sidewall portions;
depositing an electrode element fixedly connected directly to the support structure, proximate to the second end of the support structure;
forming a spring element arranged within the recess and connected to the support structure;
forming a seismic mass arranged within the recess and connected to the support structure via the spring element so that the seismic mass is displaceable with respect to the electrode element via the spring element; and
forming a capacitor having a capacitance between the seismic mass and the electrode element, wherein the capacitance of the capacitor depends on a displacement between the seismic mass and the electrode element.

2. The method according to claim 1 , the method further comprising:
etching the recess into the semiconductor substrate such that the support structure and the seismic mass are formed within a footprint of the recess by omitting the support structure and the seismic mass from being etched.

3. The method according to claim 2 , the method further comprising:
etching the recess into the semiconductor substrate using a silicon-on-nothing process or a Venezia process.

4. The method according to claim 1 , the method further comprising:
depositing a structured sacrificial layer on the seismic mass; and
depositing the electrode element on the structured sacrificial layer.

5. The method according to claim 4 , the method further comprising:
depositing a further structured sacrificial layer on the electrode element or the structured sacrificial layer;
depositing a sealing element on the further structured sacrificial layer to form a sealed capacitive microelectromechanical device;
removing the sacrificial layer or the further sacrificial layer through an opening in the sealing element; and
closing the opening in the sealing element.

6. The method according to claim 1 , wherein the electrode element is movably fixed.

7. The method according to claim 1 , wherein the seismic mass is displaceable with respect to the electrode element in the direction parallel to the sidewall portions.

8. The method according to claim 1 , wherein the support structure, the electrode element, the spring element, and the seismic mass are arranged entirely within a footprint of the recess.

9. The method according to claim 1 , wherein the semiconductor substrate, the support structure, the spring element, and the seismic mass form a unitary structure formed of a semiconductor material.

10. The method according to claim 9 , wherein the electrode element comprises a conducting material that is different from the semiconductor material.

11. The method according to claim 1 , wherein the electrode element, the support structure, the spring element, and the seismic mass are formed of polycrystalline silicon.

12. The method according to claim 1 , wherein the electrode element is a plate having an opening formed through a thickness dimension of the electrode element, the opening being configured to receive the support structure, wherein the support structure is inserted through the opening.

13. The method according to claim 12 , further comprising:
forming a sealing element over the recess and coupled to the sidewall portions of the semiconductor substrate, wherein the sealing element is configured to hermetically seal the recess such that the support structure, the electrode element, and the seismic mass are arranged within a footprint of the hermetically sealed recess,
wherein the support structure extends through the electrode element and extends to the sealing element to which the second end of the support structure is directly coupled.

14. The method according to claim 1 , further comprising:
forming a sealing element over the recess and coupled to the sidewall portions of the semiconductor substrate, wherein the sealing element is configured to hermetically seal the recess such that the support structure, the electrode element, and the seismic mass are arranged within a footprint of the hermetically sealed recess.

15. The method according to claim 14 , wherein the support structure extends through the electrode element and extends to the sealing element to which the second end of the support structure is directly coupled.

16. The method according to claim 14 , wherein the support structure is mechanically connected to the semiconductor substrate and the sealing element.

17. The method according to claim 1 , further comprising:
forming a reinforcement structure fixedly connected to the support structure, wherein the reinforcement structure is configured to reinforce the electrode element such that the electrode element is arranged in a fixed position with respect to the semiconductor substrate or the support structure.

18. The method according to claim 17 , wherein the seismic mass is structured such that a residual portion of the seismic mass forms the reinforcement structure, the method further comprise:
forming a spacer element coupled to the reinforcement structure to form a gap between the electrode element and the seismic mass such that the capacitor is formed by the electrode element and the seismic mass.

19. The method according to claim 18 , wherein the spacer element is configured to form a dielectric isolation between the electrode element and the reinforcement structure, such that the spacer element is configured to prevent charge carriers from moving from the electrode element to the reinforcement structure.

20. The method according to claim 1 , further comprising:
forming a further electrode element in the seismic mass using doping; or
forming the further electrode element on the seismic mass using deposition of a layer structure comprising an electrically conductive material.

21. The method according to claim 1 , wherein the electrode element is electrically connected to the support structure such that a sensor signal indicating a current capacitance of the capacitor or a charge of the current capacitance of the capacitor is transmitted from the capacitor, through the support structure, to the semiconductor substrate.

Assignees

• Infineon Technologies Ag

Inventors

• Kautzsch Thoralf
• Bieselt Steffen
• Froehlich Heiko
• Roeth Andre
• Stegemann Maik
• Vogt Mirko
• Winkler Bernhard

Classifications

• H10P14/40

  of conductive or resistive materials · CPC title

• H10P14/00

  Formation of materials, e.g. in the shape of layers or pillars · CPC title

• H10W20/058

  by depositing on sacrificial masks, e.g. using lift-off · CPC title

• B81C2201/0105

  Sacrificial layer · CPC title

• B81C2201/013

  Etching · CPC title