Method and device for determining a feature for devices produced on a wafer

Patent metadata

Field	Value
Publication number	US-11417552-B2
Application number	US-202017002675-A
Country	US
Kind code	B2
Filing date	Aug 25, 2020
Priority date	Oct 10, 2019
Publication date	Aug 16, 2022
Grant date	Aug 16, 2022

Abstract

A computer-implemented method for inferring a device feature of a device produced on a wafer. The method includes: providing a wafer feature model associating a wafer position indicating a position of a produced device on the wafer to a device feature, wherein the wafer feature model is configured to be trained by one or more wafer feature maps and particularly configured as a Gaussian process model, providing a sample device feature of at least one device at a sample wafer position, and inferring the device feature of at least one other device of the wafer depending on the provided wafer feature model.

First claim

What is claimed is:

1. A computer-implemented method for determining a device feature of a device produced on a wafer, comprising the following steps:
providing a wafer feature model associating a wafer position indicating a position of a produced device on the wafer to a device feature, wherein the wafer feature model is configured to be trained by one or more wafer feature maps and is configured as a Gaussian process model;
providing a sample device feature of at least one device at a sample wafer position; and
determining the device feature of at least one other device of the wafer, depending on the provided wafer feature model;
wherein the sample device feature of the at least one device is obtained at a selected discrete subset of wafer positions which is selected using active learning and which maximizes a likelihood of all samples on the wafer being inside given specification limits.

2. The method according to claim 1 , wherein the device feature includes one of: (i) an indication of functionality, or (ii) an indication of an error, or (iii) an indication whether the device fulfils a given specification, or (iv) a calibration parameter to be stored into the device.

3. The method according to claim 1 , wherein the wafer feature model additionally associates environmental conditions to the device feature and/or operating conditions to the device feature.

4. The method according to claim 1 , wherein the wafer feature model is trained by providing a number of processed wafers including identical devices, wherein the processed wafers include one or more corner lot wafers.

5. The method according to claim 1 , wherein the wafer feature model is non-parametric and provides an uncertainty value for a predicted feature.

6. The method according to claim 1 , wherein the selected discrete subset of wafer positions is selected by maximizing the likelihood of all samples on the wafer being inside given specification limits s lim according to

p
⁡

(

d
⁡

(
f
)

≤

s
lim

)

≥

p
min

wherein

d
⁡

(
f
)

=

∑

i
∈
X

⁢



f

m
⁢
o
⁢
d

⁡

(
i
)

-

f

d
⁢
e
⁢
s



and p min is a lower bound on the minimum probability that the specification limit s lim is satisfied per sample, wherein X is a set of all wafer positions, f mod is a modelled feature and f des is a nominal feature which is met for the device at the specific position i.

7. The method according to claim 6 , wherein a limit violation v is specified as

v
=

p
⁡

(

min

f

m
⁢
o
⁢
d

(
i

⁢

d
⁡

(
f
)

≤

s

a
⁢
c
⁢
c

)

wherein the subset of wafer positions is selected to minimize a probability of expected limit violations over all devices of the wafer.

8. The method according to claim 7 , wherein the set of wafer positions is updated using an acquisition function
α(χ samp )= ˜p( |χ θ,ϕ) [ v ( y samp )− y˜p( , ,χ samp , samp ,θ,ϕ) [ v ( y )]]

wherein the selecting of the wafer position for an optimized subset of wafer positions, the acquisition function is evaluated for all possible combinations of wafer positions, wherein the subset of wafer positions with a lowest expected limit violation is selected.

9. The method according to claim 6 , wherein the device feature model is provided by using a prior for the patterns of corresponding device features based on prior technological knowledge of fabrication steps using processing equipment.

10. A computer-implemented method for production of devices on a wafer, comprising the following steps:
controlling a production of the devices on one or more wafers;
determining a respective device feature for each of the devices by:
providing a wafer feature model associating a wafer position indicating a position of a produced device on the wafer to a device feature, wherein the wafer feature model is configured to be trained by one or more wafer feature maps and is configured as a Gaussian process model;
providing a sample device feature of at least one device at a sample wafer position;
determining the device feature of at least one other device of the wafer, depending on the provided wafer feature model;
wherein the sample device feature of the at least one device is obtained at a selected discrete subset of wafer positions which is selected using active learning and which maximizes a likelihood of all samples on the wafer being inside given specificati

Assignees

• Bosch Gmbh Robert

Inventors

• Zimmer Christoph
• Radovic Dusan
• Schmidt Eric Sebastian
• Kuehnel Matthias
• Herman Michael
• Liu Wenqing
• Lubisch Jan Martin

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P72/0616

  Monitoring of warpages, curvatures, damages, defects or the like · CPC title

• H10P72/0606 Primary

  Position monitoring, e.g. misposition detection or presence detection · CPC title

• H10P74/23 Primary

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P74/20

  characterised by the properties tested or measured, e.g. structural or electrical properties · CPC title