Clock data recovery in multilane data receiver

Patent metadata

Field	Value
Publication number	US-10347283-B2
Application number	US-201715802365-A
Country	US
Kind code	B2
Filing date	Nov 2, 2017
Priority date	Nov 2, 2017
Publication date	Jul 9, 2019
Grant date	Jul 9, 2019

Abstract

Methods and systems are described for obtaining, at a phase-error aggregator, a plurality of data-derived phase-error signals for two or more data lanes of a multi-wire bus, each data-derived phase-error signal generated using at least (i) a phase of one or more phases of a local oscillator signal and (ii) a corresponding data signal associated with one of the two or more data lanes, generating a composite phase-error signal representing a combination of the two or more obtained data-derived phase-error signals, receiving the composite phase-error signal at a loop filter responsively generating an oscillator control signal, and receiving the oscillator control signal at a local oscillator and responsively adjusting a timing of the local oscillator to adjust the one or more phases of the local oscillator signal.

First claim

We claim:

1. An apparatus comprising:
a plurality of sampling elements, each sampling element of the plurality of sampling elements configured to (i) receive a corresponding data signal and to responsively generate a pair of speculative DFE-corrected data samples by applying a pair of decision feedback equalization (DFE) coefficients to the corresponding data signal, the pair of speculative DFE-corrected data samples being generated at a sampling instant based on one or more phases of a local oscillator signal, (ii) select, based on a historical data sample, a first DFE-corrected data sample of the pair of DFE-corrected data samples as a data output, and a second DFE-corrected data sample of the pair of DFE-corrected data samples as a respective data-derived phase-error signal;
a phase-error aggregator configured to obtain at least two respective data-derived phase-error signals from the plurality of sampling elements and to responsively generate a composite phase-error signal representing a combination of the at least two respective data-derived phase-error signals;
a loop filter configured to receive the composite phase-error signal and to responsively generate an oscillator control signal; and
a local oscillator configured to receive the oscillator control signal and to responsively adjust a timing of the local oscillator to adjust the one or more phases of the local oscillator signal.

2. The apparatus of claim 1 , wherein the historical data sample is obtained from a data history storage element.

3. The apparatus of claim 1 , wherein the historical data sample is obtained from a sampling element of a parallel processing phase.

4. The apparatus of claim 1 , wherein the composite phase-error signal is an analog composite phase-error signal, and wherein the phase-error aggregator comprises:
a plurality of charge-pumps, each charge pump configured to receive a respective data-derived phase-error signal of the plurality of data-derived phase-error signals, the plurality of charge pumps configured to responsively generate a plurality of currents representing the data-derived phase-error signals; and
a common analog summation node configured to combine the plurality of currents to generate the analog composite phase-error signal.

5. The apparatus of claim 1 , wherein the composite phase-error signal is a digital composite phase-error signal, and wherein the phase-error aggregator comprises a combiner configured to receive the data-derived phase-error signals and to responsively generate the digital composite phase-error signal.

6. The apparatus of claim 1 , wherein the local oscillator comprises a plurality of inverter stages, wherein the oscillator control signal is configured to adjust a delay value in each inverter stage, wherein each inverter stage comprises a tunable current source configured to provide an operating current corresponding to the delay value, wherein the delay value is adjusted by adjusting a magnitude of the tunable current source.

7. The apparatus of claim 1 , wherein the phase-error aggregator is configured to combine data-derived phase-error signals that are determined to have had a transition in the corresponding data signal.

8. The apparatus of claim 1 , further comprising:
a plurality of data lane-specific error aggregators, each data lane-specific aggregator associated with a respective data lane and configured to receive data-driven phase-error signals associated with the respective data lane, each data lane-specific aggregator configured to responsively determine a respective data lane-specific control signal indicative of a data lane-specific delay value associated with the respective data lane;
a plurality of data lane-specific delay elements, each data lane-specific delay element associated with a respective data lane and configured to receive the data lane-specific control signal associated with the respective data lane, each data lane-specific delay element configured to delay the phase of the local oscillator signal used for generating each data-derived phase-error signal for the respective data lane by the associated data lane-specific delay value.

9. A method comprising:
receiving corresponding data signals at a plurality of sampling elements;
generating, for each corresponding data signal, a pair of speculative DFE-corrected data samples by applying a pair of decision feedback equalization (DFE) coefficients to the corresponding data signal, the pair of speculative DFE-corrected samples generated at a sampling instant according to a phase of one or more phases of a local oscillator signal;
selecting, based on a historical data sample, a first DFE-corrected data sample of the pair of DFE-corrected data samples as a data output, and a second DFE-corrected data sample of the pair of DFE-corrected data samples as a respective data-derived phase-error signal;
obtaining, at a phase-error aggregator, at least two respective data-derived phase-error signals;
generating a composite phase-error signal representing a combination of the at least two respective data-derived phase-error signals;
receiving the composite phase-error signal at a loop filter responsively generating an oscillator control signal; and
receiving the oscillator control signal at a local oscillator and responsively adjusting a timing of the local oscillator to adjust the one or more phases of the local oscillator signal.

10. The method of claim 9 , wherein the historical data sample is obtained from a data history element.

11. The method of claim 9 , wherein the historical data sample is obtained from a sampling element in a parallel processing phase.

12. The method of claim 9 , wherein the phase of the local oscillator signal used for generating each data-derived phase-error signal for a given data lane is delayed by a data lane-specific delay value.

13. The method of claim 9 , further comprising determining respective data lane-specific control signals indicative of the data lane-specific delay value, each data lane-specific control signal generated using a respective data lane-specific error aggregator operating on respective data-driven phase-error signals from an associated data lane.

14. The method of claim 9 , generating the composite phase-error signal comprises:
receiving, at a plurality of charge-pumps, the plurality of data-derived phase-error signals, and responsively generating a plurality of currents representing the data-derived phase-error signals; and
combining, at a common analog summation node, the plurality of currents to generate the composite phase-error signal.

15. The method of claim 9 , wherein generating the composite phase-error signal comprises performing a digital combination of the plurality of data-derived phase-error signals.

16. The method of claim 9 , wherein data-derived phase-error signals having been determined to have had a transition in the corresponding data signal are combined to generate the composite phase-error signal.

Assignees

• Kandou Labs SA

Inventors

• Hormati Ali
• Tajalli Armin

Classifications

• H04L25/14

  Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• G06F13/4063

  Device-to-bus coupling · CPC title

• G06F15/82

  data or demand driven · CPC title

• H04L7/0337

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title