Oversampling CDR which compensates frequency difference without elasticity buffer

Patent metadata

Field	Value
Publication number	US-9832008-B2
Application number	US-201514986152-A
Country	US
Kind code	B2
Filing date	Dec 31, 2015
Priority date	Mar 31, 2014
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.

First claim

The invention claimed is:

1. A method, comprising:
receiving a data signal;
generating a first clock signal having a first frequency;
detecting a phase shift of the data signal with respect to the first clock signal;
outputting from a programmable frequency divider a divided clock signal having a second frequency based on the first frequency and a division ratio;
adjusting the division ratio when the phase shift surpasses a threshold value P TH ;
adjusting the division ratio from a base value for one or more clock cycles when the phase shift is greater than the threshold value P TH ;
returning the division ratio to the base value; and
decreasing the division ratio to a low value when the phase shift indicates that the first frequency is lower than a frequency of the data signal.

2. A method, comprising:
receiving a data signal;
generating a first clock signal having a first frequency;
detecting a phase shift of the data signal with respect to the first clock signal;
outputting from a programmable frequency divider a divided clock signal having a second frequency based on the first frequency and a division ratio;
adjusting the division ratio when the phase shift surpasses a threshold value P TH ;
adjusting the division ratio from a base value for one or more clock cycles when the phase shift is greater than the threshold value P TH ;
returning the division ratio to the base value;
decreasing the division ratio to a low value when the phase shift indicates that the first frequency is lower than a frequency of the data signal; and
increasing the division ratio to a high value when the phase shift indicates that the first frequency is higher than the frequency of the data signal.

3. A method, comprising:
receiving a data signal;
generating a first clock signal having a first frequency;
detecting a phase shift of the data signal with respect to the first clock signal;
outputting from a programmable frequency divider a divided clock signal having a second frequency based on the first frequency and a division ratio;
adjusting the division ratio when the phase shift surpasses a threshold value P TH ;
adjusting the division ratio from a base value for one or more clock cycles when the phase shift is greater than the threshold value P TH ;
returning the division ratio to the base value; and
decreasing the division ratio to a low value when the phase shift indicates that the first frequency is lower than a frequency of the data signal,
wherein the low value is equal to the base value minus 1.

4. A method, comprising:
receiving a data signal;
generating a first clock signal having a first frequency;
detecting a phase shift of the data signal with respect to the first clock signal;
outputting from a programmable frequency divider a divided clock signal having a second frequency based on the first frequency and a division ratio;
adjusting the division ratio when the phase shift surpasses a threshold value P TH ;
adjusting the division ratio from a base value for one or more clock cycles when the phase shift is greater than the threshold value P TH ;
returning the division ratio to the base value;
decreasing the division ratio to a low value when the phase shift indicates that the first frequency is lower than a frequency of the data signal; and
increasing the division ratio to a high value when the phase shift indicates that the first frequency is higher than the frequency of the data signal,
wherein the high value is equal to the base value plus 1.

5. The method of claim 4 wherein the threshold value P TH is greater than one half cycle of the first clock signal.

6. The method of claim 5 wherein the threshold value P TH is less than one cycle of the first clock signal.

7. A clock and data recovery circuit, comprising:
a clock, which, in operation, generates a first clock signal having a first frequency; and
a programmable frequency divider, which, in operation, outputs a divided clock signal having a second frequency based on the first frequency and a division ratio, and adjusts the division ratio when a phase shift of a received data signal with respect to the first clock signal surpasses a threshold value P TH ,
wherein the programmable frequency divider, in operation, adjusts the division ratio from a base value for one or more clock cycles when the phase shift is greater than the threshold value P TH , and returns the division ratio to the base value, and
wherein the programmable frequency divider, in operation, decreases the division ratio to a low value when the phase shift indicates that the first frequency is lower than a frequency of the data signal.

8. The clock and data recovery circuit of claim 7 wherein the programmable frequency divider, in operation, increases the division ratio to a high value when the phase shift indicates that the first frequency is higher than the frequency of the data signal.

9. The clock and data recovery circuit of claim 8 wherein the high value is equal to the base value plus 1.

10. The clock and data recovery circuit of claim 7 wherein the low value is equal to the base value minus 1.

11. The clock and data recovery circuit of claim 7 wherein the threshold value P TH is greater than one half cycle of the first clock signal.

12. The clock and data recovery circuit of claim 11 wherein the threshold value P TH is less than one cycle of the first clock signal.

13. A clock and data recovery circuit, comprising:
reception means for receiving a data signal;
clock means for generating a first clock signal having a first frequency;
detection means for detecting a phase shift of the data signal with respect to the first clock signal; and
frequency dividing means for outputting a divided clock signal having a second frequency based on the first frequency and a division ratio, and adjusts the division ratio when the phase shift surpasses a threshold value P TH ,
wherein the frequency dividing means adjusts the division ratio from a base value for one or more clock cycles when the phase shift is greater than the threshold value P TH , and returns the division ratio to the base value, and
wherein the frequency dividing means decreases the division ratio to a low value when the phase shift indicates that the first frequency is lower than a frequency of the data signal, the low value being equal to the base value minus 1, and increases the division ratio to a high value when the phase shift indicates that the first frequency is higher than the frequency of the data signal, the high value being equal to the base value plus 1.

14. The clock and data recovery circuit of claim 13 wherein the threshold value P TH is greater than one half cycle of the first clock signal.

Assignees

• St Microelectronics Int Nv

Inventors

• Chowdhary Abhishek
• Uppal Vivek
• Kaushik Alok
• Mandal Sajal Kumar
• Nandy Tapas
• Chopra Sanjeev

Classifications

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H04L7/0004

  Initialisation of the receiver (H04L7/0075 and H04L7/10 take precedence) · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H04L7/005

  Correction by an elastic buffer · CPC title

• H04L25/03057

  with a recursive structure (H04L25/03031 takes precedence) · CPC title