Semiconductor packages with thin die and related methods

Patent metadata

Field	Value
Publication number	US-11404276-B2
Application number	US-202016879251-A
Country	US
Kind code	B2
Filing date	May 20, 2020
Priority date	Aug 17, 2017
Publication date	Aug 2, 2022
Grant date	Aug 2, 2022

Abstract

Implementations of a semiconductor device may include a semiconductor die including a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof where the semiconductor die may be coupled with one of a substrate, a leadframe, an interposer, a package, a bonding surface, or a mounting surface. The thickness may be between 0.1 microns and 125 microns.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and
one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof;
wherein the first largest planar surface, the second largest planar surface, and the thickness are formed by at least two singulated semiconductor die coupled through a common die street; and
wherein the at least two singulated semiconductor die are coupled to one of a substrate, a leadframe, an interposer, a package, a bonding surface, or a mounting surface and
wherein a warpage of the at least two singulated semiconductor die is less than 200 microns.

2. The device of claim 1 , wherein the thickness is between 0.1 microns and 125 microns.

3. The device of claim 1 , wherein a perimeter of the at least two singulated semiconductor die is rectangular and a size of the at least two singulated semiconductor die is at least 6 mm by 6 mm to 211 mm by 211 mm.

4. The device of claim 1 , wherein a perimeter of the at least two singulated semiconductor die comprises a closed shape and wherein the one of the permanent die support structure, the temporary die support structure, or any combination thereof comprises a perimeter comprising a closed shape.

5. The device of claim 1 , further comprising one of a second permanent die support structure or a temporary die support structure coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof.

6. The device of claim 1 , wherein the one of the permanent die support structure, the temporary die support structure, or any combination thereof comprises two or more layers.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Carney Francis J
• Chew Chee Hiong
• Wang Soon Wei
• Kurose Eiji

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/879

  Bump connectors and bond wires · CPC title

• H10W72/5434

  the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title