Laser ablation for package fabrication

Patent metadata

Field	Value
Publication number	US-11400545-B2
Application number	US-202016871302-A
Country	US
Kind code	B2
Filing date	May 11, 2020
Priority date	May 11, 2020
Publication date	Aug 2, 2022
Grant date	Aug 2, 2022

Abstract

A method of fabricating a frame to enclose one or more semiconductor dies includes forming one or more features including one or more cavities and one or more through-vias in a substrate by a first laser ablation process, filling the one or more through-vias with a dielectric material, and forming a via-in-via in the dielectric material filled in each of the one or more through-vias by a second laser ablation process. The one or more cavities is configured to enclose one or more semiconductor dies therein. In the first laser ablation process, frequency, pulse width, and pulse energy of a first pulsed laser beam to irradiate the substrate are tuned based on a depth of the one or more features. In the second laser ablation process, frequency, pulse width, and pulse energy of a second pulsed laser beam to irradiate the dielectric material are tuned based on a depth of the via-in-via.

First claim

What is claimed is:

1. A method of fabricating a frame to enclose one or more semiconductor dies, comprising:
forming one or more features in a substrate by a first laser ablation process, the one or more features comprising:
one or more cavities configured to enclose one or more semiconductor dies therein; and
one or more through-vias extending through the substrate;

filling the one or more through-vias with a dielectric material; and
forming a via-in-via in the dielectric material filled in each of the one or more through-vias by a second laser ablation process, wherein:
in the first laser ablation process, frequency, pulse width, and pulse energy of a first pulsed laser beam to irradiate the substrate are tuned based on a depth of the one or more features, and
in the second laser ablation process, frequency, pulse width, and pulse energy of a second pulsed laser beam to irradiate the dielectric material are tuned based on a depth of the via-in-via.

2. The method of claim 1 , wherein the substrate comprises silicon.

3. The method of claim 2 , wherein:
the one or more cavities have a lateral dimension of between 3 mm and 50 mm and a depth of between 50 μm and 200 μm, and
the first pulsed laser beam is tuned to have the frequency of 5 kHz and 40 kHz, the pulse energy of between 0.5 mJ and 4.5 mJ, and the pulse width of between 15 ns and 600 ns.

4. The method of claim 2 , wherein:
the one or more through-vias have a diameter between 50 μm and 200 μm, and
the via-in-via in each of the one or more through-vias has a diameter of between 20 μm and 70 μm.

5. The method of claim 4 , wherein:
the substrate has a thickness of between 100 μm and 200 μm, and
the first pulsed laser beam is tuned to have the frequency of between 5 kHz and 100 kHz, the pulse energy of between 0.5 mJ and between 4.5 mJ, and the pulse width of between 100 ns and 1200 ns.

6. The method of claim 5 , wherein:
the second pulsed laser beam is tuned to have the frequency of between 10 kHz and 1000 kHz, the pulse energy of between 25 μJ and between 250 μJ, and the pulse width of between 3 ns and 60 ns.

7. The method of claim 4 , wherein:
the substrate has a thickness of between 500 μm and 1 mm, and
the first pulsed laser beam is tuned to have the frequency of between 5 kHz and 30 kHz, the pulse energy of between 2 mJ and 10 mJ, and the pulse width of between 1 μs and 5 μs.

8. The method of claim 7 , wherein:
the second pulsed laser beam is tuned to have the frequency of between 5 kHz and 100 kHz, the pulse energy of between 0.1 mJ and between 0.4 mJ, and the pulse width of between 3 ns and 60 ns.

9. A method of patterning a substrate, comprising:
forming one or more features in a substrate by irradiating the substrate with a pulsed laser beam, wherein the substrate comprises silicon, and wherein the one or more features have a diameter between 50 μm and 200 μm and a depth of between 100 μm and 200 μm; and
tuning frequency, pulse width, and pulse energy of the pulsed laser beam based on a depth of the one or more features, wherein the pulsed laser beam is tuned to have the frequency of between 5 kHz and 100 kHz, the pulse energy of between 0.5 mJ and between 4.5 mJ, and the pulse width of between 100 ns and 1200 ns.

10. The method of claim 9 , wherein
a sub-set of the one or more features is formed by on-the-fly drilling.

11. A method of patterning a substrate, comprising:
forming one or more features in a substrate by irradiating the substrate with a pulsed laser beam, wherein the substrate comprises silicon, and wherein the one or more features have a diameter between 50 μm and 200 μm and a depth of between 500 μm and 1 mm; and
tuning frequency, pulse width, and pulse energy of the pulsed laser beam based on a depth of the one or more features, wherein the pulsed laser beam is tuned to have the frequency of between 5 kHz and 30 kHz, the pulse energy of between 2 mJ and 10 mJ, and the pulse width of between 1 μs and 5 μs.

12. The method of claim 11 , wherein
a sub-set of the one or more features is formed by on-the-fly drilling.

13. A method of patterning a substrate, comprising:
forming one or more features in a substrate by irradiating the substrate with a pulsed laser beam, wherein the substrate comprises silicon, and wherein the one or more features have a lateral dimension of between 3 mm and 50 mm and a depth of between 50 μm and 200 μm; and
tuning frequency, pulse width, and pulse energy of the pulsed laser beam based on a depth of the one or more features, wherein the pulsed laser beam is tuned to have the frequency of 5 kHz and 40 kHz, the pulse energy of between 0.5 mJ and 4.5 mJ, and the pulse width of between 15 ns and 600 ns.

14. The method of claim 13 , wherein
a sub-set of the one or more features is formed by on-the-fly drilling.

15. A method of fabricating a die assembly, comprising:
forming a frame, comprising:
forming one or more features in a substrate by a first laser ablation process, the one or more features comprising one or more cavities and one or more through-vias extending through the substrate;
filling the one or more through-vias with a dielectric material; and
forming a via-in-via in the dielectric material filled in each of the one or more through-vias by a second laser ablation process;

disposing one or more semiconductor dies within the one or more cavities; and
disposing an interconnection within the via-in-via, wherein:
in the first laser ablation process, frequency, pulse width, and pulse energy of a first pulsed laser beam to irradiate the substrate are tuned based on a depth of the one or more features, and
in the second laser ablation process, frequency, pulse width, and pulse energy of a second pulsed laser beam to irradiate the dielectric material are tuned based on a depth of the via-in-via.

16. The method of claim 15 , wherein the substrate comprises silicon.

17. The method of claim 16 , wherein:
the one or more cavities have a lateral dimension of between 3 mm and 50 mm and a depth of between 50 μm and 200 μm, and
the first pulsed laser beam is tuned to have the frequency of 5 kHz and 40 kHz, the pulse energy of between 0.5 mJ and 4.5 mJ, and the pulse width of between 15 ns and 600 ns.

18. The method of claim 16 , wherein:
the one or more through-vias have a diameter between 50 μm and 200 μm, and
the via-in-via in each of the one or more through-vias has a diameter of between 20 μm and 70 μm.

19. The method of claim 18 , wherein:
the substrate has a thickness of between 500 μm and 1 mm, and
the first pulsed laser beam is tuned to have the frequency of between 5 kHz and 30 kHz, the pulse energy of between 2 mJ and 10 mJ, and the pulse width of between 1 μs and 5 μs.

20. The method of claim 19 , wherein:
the second pulsed laser beam is tuned to have the frequency of between 5 kHz and 100 kHz, the pulse energy of between 0.1 mJ and between 0.4 mJ, and the pulse width of between 3 ns and 60 ns.

Assignees

• Applied Materials Inc

Inventors

• Leschkies Kurtis
• Lei Wei-Sheng
• Franklin Jeffrey L
• Delmas Jean
• Chen Han-Wen
• Park Giback
• Verhaverbeke Steven

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title