Method of forming an electrode on a substrate and a semiconductor device structure including an electrode

Patent metadata

Field	Value
Publication number	US-11398382-B2
Application number	US-202017038514-A
Country	US
Kind code	B2
Filing date	Sep 30, 2020
Priority date	Mar 27, 2018
Publication date	Jul 26, 2022
Grant date	Jul 26, 2022

Abstract

A method of forming an electrode on a substrate is disclosed. The method may include: contacting the substrate with a first vapor phase reactant comprising a titanium tetraiodide (TiI4) precursor; contacting the substrate with a second vapor phase reactant comprising a nitrogen precursor; and depositing a titanium nitride layer over a surface of the substrate thereby forming the electrode; wherein the titanium nitride layer has an electrical resistivity of less than 400 μΩ-cm. Related semiconductor device structures including a titanium nitride electrode deposited by the methods of the disclosure are also provided.

First claim

What is claimed is:

1. A method comprising:
providing a substrate within a reaction chamber;
forming a first electrode overlying the substrate, the step of forming the first electrode comprising:
heating the substrate to a temperature of less than 300° C.;
contacting the substrate with a first vapor phase reactant comprising a titanium tetraiodide precursor (TiI 4 );
contacting the substrate with a second vapor phase reactant comprising a nitrogen precursor; and
depositing a titanium nitride layer over a surface of the substrate thereby forming the first electrode;

forming a dielectric structure overlying the first electrode; and
forming a second electrode overlying the dielectric structure at a substrate temperature of less than 300° C., wherein the forming of the second electrode comprises performing the contacting steps and the depositing step to form a second titanium nitride layer.

2. The method of claim 1 , wherein dielectric structure comprises a multilayer dielectric structure.

3. The method of claim 2 , wherein the multilayer dielectric structure comprises a ZrO 2 /Al 2 O 3 /ZrO 2 structure.

4. The method of claim 1 , wherein the nitrogen precursor comprises at least one of ammonia (NH 3 ), hydrazine (N 2 H 4 ), triazane (N 3 H 5 ), tertbutylhydrazine (C 4 H 9 N 2 H 3 ), methylhydrazine (CH 3 NHNH 2 ), dimethylhydrazine ((CH 3 ) 2 N 2 H 2 ), and a nitrogen containing plasma.

5. The method of claim 1 , wherein the temperature is less than 250° C.

6. The method of claim 1 , wherein the titanium nitride layer has an average r.m.s. surface roughness (Ra) of less than 2 Angstroms.

7. The method of claim 1 , wherein the titanium nitride layer has a density greater than 5.4 g/cm3.

8. The method of claim 1 , wherein the titanium nitride layer has an electrical resistivity of less than 150 μΩ-cm at a thickness of less than 40 Angstroms.

9. The method of claim 1 , wherein the titanium nitride layer comprises an XRD peak intensity ratio <111>:<200> of greater than 2:1.

10. The method of claim 1 , wherein the titanium nitride layer is deposited with a step coverage of greater than 95%.

11. The method of claim 1 , wherein the substrate, the first electrode, and the dielectric structure are provided in a dynamic random access memory (DRAM) device structure.

12. The method of claim 11 , wherein the titanium nitride layer comprises a bottom electrode to the DRAM device.

13. A semiconductor device structure, the structure comprising:
a titanium nitride electrode; and
a dielectric structure disposed overlying the titanium nitride electrode,
wherein the titanium nitride electrode has an electrical resistivity of less than 400 μΩ-cm, and
wherein the semiconductor device structure is formed according to the method of claim 1 .

14. The structure of claim 13 , wherein the titanium nitride electrode has an average r.m.s. surface roughness (Ra) of less than 2 Angstroms.

15. The structure of claim 13 , wherein the titanium nitride electrode has an electrical resistivity of less than 150 μΩ-cm at a thickness of less than 40 Angstroms.

16. The structure of claim 13 , further comprising a second titanium nitride electrode overlying the dielectric structure.

17. The structure of claim 16 , wherein the semiconductor device structure comprises a dynamic random access memory (DRAM) device structure.

18. The structure of claim 17 , wherein the titanium nitride electrode comprises a bottom electrode to the DRAM device structure.

Assignees

• Asm Ip Holding Bv

Inventors

• Mousa Moataz Bellah
• Hsu Peng-Fu
• Johnson Ward
• Raisanen Petri

Classifications

• H10D64/669

  the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN · CPC title

• H10D84/83135

  the IGFETs characterised by having different gate conductor materials or different gate conductor implants · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10P14/69394

  the material containing titanium, e.g. TiO2 · CPC title