Memory device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-11387337-B2
Application number	US-202017134131-A
Country	US
Kind code	B2
Filing date	Dec 24, 2020
Priority date	Jan 13, 2019
Publication date	Jul 12, 2022
Grant date	Jul 12, 2022

Abstract

A memory device includes a main cell on a substrate, a first reference cell adjacent to one side of the main cell, and a second reference cell adjacent to another side of the main cell. Preferably, the main cell includes a first gate electrode on the substrate, a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode, a first charge trapping layer between the first gate electrode and the second gate electrode and including a first oxide-nitride-oxide (ONO) layer, a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode, and a second charge trapping layer between the first gate electrode and the third gate electrode and including a second ONO layer.

First claim

What is claimed is:

1. A memory device, comprising:
a main cell on a substrate, wherein the main cell comprises:
a first gate electrode on the substrate;
a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode;
a first charge trapping layer between the first gate electrode and the second gate electrode, wherein the first charge trapping layer comprises a first oxide-nitride-oxide (ONO) layer;
a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode; and
a second charge trapping layer between the first gate electrode and the third gate electrode, wherein the second charge trapping layer comprises a second ONO layer;

a first reference cell adjacent to one side of the main cell; and
a second reference cell adjacent to another side of the main cell
a first contact plug directly contacting the first gate electrode;
a second contact plug directly contacting the second gate electrode; and
a third contact plug directly contacting the third gate electrode, wherein a bottom surface of the first contact plug is lower than a bottom surface of the second contact plug and a bottom surface of the third contact plug.

2. The memory device of claim 1 , wherein the first reference cell comprises:
a fourth gate electrode on the substrate;
a fifth gate electrode on one side of the fourth gate electrode and covering a top surface of the fourth gate electrode;
a third charge trapping layer between the fourth gate electrode and the fifth gate electrode, wherein the third charge trapping layer comprises a third ONO layer;
a sixth gate electrode on another side of the fourth gate electrode and covering the top surface of the fourth gate electrode; and
a fourth charge trapping layer between the fourth gate electrode and the sixth gate electrode, wherein the fourth charge trapping layer comprises a fourth ONO layer.

3. The memory device of claim 2 , further comprising:
a fourth contact plug directly contacting the fourth gate electrode;
a fifth contact plug directly contacting the fifth gate electrode; and
a sixth contact plug directly contacting the sixth gate electrode, wherein a bottom surface of the fourth contact plug is lower than a bottom surface of the fifth contact plug and a bottom surface of the sixth contact plug.

4. The memory device of claim 2 , wherein the second reference cell comprises:
a seventh gate electrode on the substrate;
an eighth gate electrode on one side of the seventh gate electrode and covering a top surface of the seventh gate electrode;
a fifth charge trapping layer between the seventh gate electrode and the eighth gate electrode, wherein the fifth charge trapping layer comprises a fifth ONO layer;
a ninth gate electrode on another side of the seventh gate electrode and covering the top surface of the seventh gate electrode; and
a sixth charge trapping layer between the seventh gate electrode and the ninth gate electrode, wherein the sixth charge trapping layer comprises a sixth ONO layer.

5. The memory device of claim 4 , further comprising:
a seventh contact plug directly contacting the seventh gate electrode;
an eighth contact plug directly contacting the eighth gate electrode, and
a ninth contact plug directly contacting the ninth gate electrode, wherein a bottom surface of the seventh contact plug is lower than a bottom surface of the eighth contact plug and a bottom surface of the ninth contact plug.

6. The memory device of claim 4 , further comprising:
a first source/drain region between the second gate electrode and the sixth gate electrode; and
a second source/drain region between the third gate electrode and the eighth gate electrode.

Assignees

• United Microelectronics Corp

Inventors

• Huang Chun-Sung
• Wang Shen-De
• Hsu Chia-Ching
• Xiang Wang

Classifications

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/696 Primary

  having at least one additional gate, e.g. program gate, erase gate or select gate · CPC title

• H01L29/401

  Electricity · mapped topic