Discrete power transistor package having solderless DBC to leadframe attach

Patent metadata

Field	Value
Publication number	US-11387162-B2
Application number	US-202016896594-A
Country	US
Kind code	B2
Filing date	Jun 9, 2020
Priority date	Jan 5, 2012
Publication date	Jul 12, 2022
Grant date	Jul 12, 2022

Abstract

A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.

First claim

We claim:

1. A method comprising:
attaching a first metal layer of a direct-bonded copper (“DBC”) substrate to at least one lead with an ultrasonic weld to form an assembly, wherein the ultrasonic weld mechanically and electrically couples the first metal layer to the lead, wherein the DBC substrate comprises an insulative layer disposed between the first metal layer and a second metal layer,
wherein the at least one lead comprises a contact pad, having an upper surface and a lower surface, wherein the at least one lead is joined to the first metal layer through the lower surface of the contact pad, and wherein the ultrasonic weld comprises applying an ultrasonic head to the upper surface of the contact pad, wherein a plurality of non-planar structures are generated on the upper surface;
attaching a power semiconductor integrated circuit die to the first metal layer of the assembly;
surrounding at least the first metal layer and the power semiconductor integrated circuit die with an amount of encapsulant;
leaving at least a portion of the second metal layer of the DBC substrate exposed to form a back side of a packaged power integrated circuit device; and
leaving a portion of the lead exposed, wherein the second metal layer is electrically insulated from the first metal layer.

2. The method of claim 1 , wherein the packaged power integrated circuit device conforms to a TO-247 package outline.

3. The method of claim 1 , wherein the ultrasonic weld is formed by clamping the DBC substrate and the at least one lead together with not more than about 0.05 Mpa.

4. The method of claim 1 , wherein the ultrasonic weld is formed using ultrasonic vibrations of an amplitude of less than approximately 20 micrometers.

5. The method of claim 1 , wherein the ultrasonic weld decreases a thickness of a region of the first metal layer in contact with the at least one lead by about 0.05 millimeters.

6. The method of claim 1 , wherein the first metal layer has a thickness of at least 0.25 millimeters.

7. The method of claim 1 , the attaching comprising attaching one and only one power semiconductor integrated circuit die.

Assignees

• Ixys Llc
• Littelfuse Inc

Inventors

• Jeun Gi-Young
• Choi Kang Rim

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title